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IT Project Manager | Cards and Payments Payment System | Global PayPlus
Job Location:
Job Location:
San Jose, CA - USA
Monthly Salary:
Not provided by the employer
Monthly Salary:
Posted:
1 July 2026 (30+ days ago)
Posted:
Application Deadline:
28 September 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Job Title ASIC Engineering Technical Lead
Work Location & Reporting Address San Jose CA 95134
Vendor Rate $
Contract duration 6
Target Start Date 12 Jun 2026
Job Details:
Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
Design & implement robust and reusable RTL with CDC/RDC considerations
Spec comprehensive CDC/RDC check flows and work with CAD team to implement
Review and approve CDC/RDC constraints and waivers
Perform static glitch analysis
Improve design with prevention of static glitch harzad
Bachelors or Masters degree on Electrical Engineering with at least 10 years of experience on ASIC chip design
RTL development skills and experiences
Solid understanding on CDC/RDC concepts and relevant design implementation
Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists
Preferred Qualifications
Experiences on Static Timing Analysis
Experiences on VCS simulation SVA (SystemVerilog Assertions)
Rate 90/hour.
Minimum years of experience
>10 years
Certifications Needed :No
Top 3 responsibilities you would expect the Subcon to shoulder and execute
Lead the CDCRDC Clock Domain Crossing Reset Domain Crossing methodology in silicon one chips Design implement robust and reusable RTL with CDCRDC considerations Spec comprehensive CDCRDC check flows and work with CAD team to implement Review and approve CDCRDC constraints and waivers Perform static glitch analysis Improve design with prevention of static glitch harzad
Interview Process (Is face to face required) No Project Code :Autotest Operations
Work Location & Reporting Address San Jose CA 95134
Vendor Rate $
Contract duration 6
Target Start Date 12 Jun 2026
Job Details:
Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
Design & implement robust and reusable RTL with CDC/RDC considerations
Spec comprehensive CDC/RDC check flows and work with CAD team to implement
Review and approve CDC/RDC constraints and waivers
Perform static glitch analysis
Improve design with prevention of static glitch harzad
Bachelors or Masters degree on Electrical Engineering with at least 10 years of experience on ASIC chip design
RTL development skills and experiences
Solid understanding on CDC/RDC concepts and relevant design implementation
Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists
Preferred Qualifications
Experiences on Static Timing Analysis
Experiences on VCS simulation SVA (SystemVerilog Assertions)
Rate 90/hour.
Minimum years of experience
>10 years
Certifications Needed :No
Top 3 responsibilities you would expect the Subcon to shoulder and execute
Lead the CDCRDC Clock Domain Crossing Reset Domain Crossing methodology in silicon one chips Design implement robust and reusable RTL with CDCRDC considerations Spec comprehensive CDCRDC check flows and work with CAD team to implement Review and approve CDCRDC constraints and waivers Perform static glitch analysis Improve design with prevention of static glitch harzad
Interview Process (Is face to face required) No Project Code :Autotest Operations
