IC Packaging Design Engineer

Location: Chandler Arizona OR Hillsboro Oregon (Onsite)

Employment: Long-Term Contract (12 Months)

Experience: 4 6 Years

We are seeking an IC Packaging Design Engineer with experience in advanced semiconductor package design and substrate layout. The role involves package implementation using Siemens Xpedition or Cadence APD while ensuring signal integrity power integrity manufacturability and design rule compliance.

The engineer will work closely with cross-functional hardware package SI/PI and manufacturing teams throughout the package design lifecycle.

• Develop IC package layouts for advanced semiconductor devices.
• Create substrate designs using Siemens Xpedition (XPD) or Cadence APD.
• Implement package physical design following engineering specifications.
• Collaborate with SI/PI teams during package implementation.
• Perform substrate routing fanout planning and escape routing.
• Ensure compliance with package design rules and manufacturing requirements.
• Support design reviews and engineering change implementation.
• Coordinate with hardware PCB and package engineers.
• Optimize package layout for electrical and mechanical performance.
• Support package release documentation.
• Participate in design verification and issue resolution.
• Contribute to yield and reliability improvements.

• Bachelors or Masters degree in Electrical or Electronics Engineering.
• 4 6 years of experience in IC Packaging Design.
• Experience in advanced semiconductor package layout.
• Strong understanding of substrate design methodologies.
• Experience working in cross-functional semiconductor teams.

• Siemens Xpedition (Mentor Graphics XPD)
• Cadence Allegro
• Cadence Advanced Package Designer (APD)
• Cadence SiP

• IC Package Design
• Substrate Layout
• Package Routing
• Escape Routing
• Fanout Planning

• Physical Layout
• Design Rule Check (DRC)
• Manufacturing Rules
• Package Stack-up

• Signal Integrity (SI)
• Power Integrity (PI)
• Yield Optimization
• Reliability Design