Front-End Implementation (Synthesis) Engineer

Imagine working in a team where the only limits are the laws of physics and your imagination. nnAt Apple phenomenal ideas have a way of becoming phenomenal products and customer experiences very quickly. Bring passion and dedication to your job and theres no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices. nnJoin the team that optimises and delivers world class GPUs into Apple Silicon. As part of the GPU Front End Implementation team youll be responsible for crafting and building a GPU that enriches the lives of millions of people every day. nJoin us!

Candidates will be responsible for PPA optimisation of the netlist working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration you will deliver the outstanding GPUs for the best consumer products. nnIf youre ready to help chart the future of Apple Silicon we would love to talk to you.

Minimum of BSc in in Verilog and/or System Verilog and scripting with physical synthesis including logic and PPA optimisation techniques.

Understanding and application of physical design and static timing analysis with DFT with reset domain multi-clock domain multi-power domain (UPF) linting tools and concepts across RTL and implementing ECOs for functionality and to analyze critical paths and guide RTL designs to efficient using logic equivalence tools for RTL and Gate-level optimally with IP teams spanning multiple sites.