FPGA Design Engineer (MTD, San Jose, CA)

Our Purpose
TERADYNE where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovateandlearnsomething new every day.

We cultivate aculture of inclusion for all employees thatrespectstheir individual strengths views and experiences. We believe that our differences enable us to be a better team one that makes better decisions drivesinnovationand delivers better business results.

Opportunity Overview

Teradynes Memory Test Division (MTD)seeksamotivated and technically driven FPGA Engineerto support the development of our growing portfolio ofcutting-edgememory test solutions.

MTD creates advanced solutions for complex testingapplications driving innovation through creativity and diverse perspectives. Our test instrumentation supports the worlds most advancedmemory technologies combiningstate-of-the-artdigital and analog designscutting-edgeASIC/FPGA technologies liquid cooling and high-performance signal delivery.

We are looking for an FPGA Design Engineer withexceptional technical skills anda strong desireto collaborate on team-oriented projects. Success in this role means delivering high-quality reliable products to market quickly. If you are excited to join a dynamic global team Teradyne may be the place for you!

• Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.

• Providetechnicalguidanceto junior engineers

• Turn abstract concepts and customer requirements into reliable extensible and supportable designs.

• Assistin the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.

• Maintain schedule commitments and deliverhigh qualityend products.

• Occasional travel may berequired.

All About You
We seek individuals who share our passion. Our commitment to customer success drives us to go the extra mile. Ifyoureready to join us in this mission take a closer look at theminimumcriteria for the position.

• Bachelors Degree or equivalent in Electrical Engineering or a closely related field with a minimum of 5 years of relevant work experience or Masters Degree or equivalent with a minimum of 3 years of relevant work experience.

• Experience with Digital Design and Architecture

• RTL coding synthesis timingclosureand lab validation

• Experience with Static Timing Analysis of ASICs or FPGAs

• Experience with digital simulation testbench creation

• Experience with C or C

• Familiarity with lab equipment such as oscilloscopes power supplies and waveform generators.

Additional Desired Skills

• FPGA Transceiver based design experience

• Experience with DRAM and Flash Memory interfaces

• Experience withAltera/AMDFPGA tool flows

• Proficiencywith Verilog HDL Language

• Familiarity with UVM Methodology

• Scripting languages experience

• Linux and Windows operating systems experience

• Familiarity with ATE instrumentation

Compensation:
The base salary range for this role is $135400 - $216600. This range is a good faith estimate and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan:This job is eligible for discretionary bonus(es) based on financial performance.

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs including medical dental vision Flexible Spending Accounts retirement savings plans life and disability insurance paid vacation & holidays tuitionassistanceprograms and more. Please clickhereto see details.

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