Formal Verification Engineer


Job Location:

San Jose, CA - USA

Monthly Salary: Not Disclosed
Posted on: 6 hours ago
Vacancies: 1 Vacancy

Job Summary

Job Description:

We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools.

Key Responsibilities:

  • Develop formal verification strategies and methodologiesWrite SystemVerilog Assertions (SVA)
  • Perform property checking equivalence checking and CDC/RDC analysis
  • Identify corner cases missed in simulation
  • Collaborate with RTL teams for design improvements

Required Skills:

  • Strong knowledge of formal verification tools (Jasper VC Formal etc.)
  • Expertise in SVA and property specification
  • Solid understanding of digital design and logic reasoning

Good to Have:

  • Experience in low-power/CDC verification
  • Exposure to security verification
Job Description: We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools. Key Responsibilities: Develop formal verification strategies and methodologiesWrite SystemVerilog Assertions (SVA) Perform property chec...