FE RTL Infrastructure CAD Engineer

Do you love building elegant solutions to highly complex challenges As part of our Silicon Technologies group youll help design and manufacture our next-generation high-performance power-efficient processor system-on-chip (SoC). Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youll be responsible for crafting and building the technology that fuels Apples devices. Together you and your team will enable our customers to do all the things they love with their devices!

As a Front-End (FE) RTL Infrastructure - CAD Engineer you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use for modifying analyzing and verifying RTL. nnIn this role you will support RTL gatekeeping infrastructure of design and verification collateral as well as soft IP development and release methodologies. Additionally you will contribute to Perforce administration ensuring the integrity and performance of our version control ecosystem. You will have the opportunity to maintaining a centralized configuration management system that enables different design views to be loaded into any Front-End important key aspect of this position is driving innovation through building generative AI solutions across all of these systems and identifying opportunities where AI can accelerate engineering productivity and improve infrastructure reliability. You role will also involve managing internal training materials keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust scalable infrastructure solutions across RTL Design and DV teams within Apples HWTech short this position focuses in fostering our North Star and making sure that our vision statement extends across the different design groups:n To create monitor and maintain high quality infrastructure and flows that enable Apple Silicon to produce chips that enable Apples best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apples chip design efforts.

Minimum of BS degree 10 years of relevant experiencenExpertise in programming in Python or PerlnKnowledge in Verilog and SystemVerilog

Experience with Front-End EDA tools such as Clock Domain Crossing Reset Domain Crossing or LintnUnderstanding of Front-End RTL Build or Construction flowsnExcellent communication debug and root causing skillsnCustomer-oriented mindset and support experiencenExperience in leading large-scale software system development from specification to deploymentnMSEE/CE/CS preferred