Custom Timing and Verification CAD Engineer

Apples custom silicon is among the most sophisticated in the world and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom Timing CAD team builds and owns the flows tools and methodologies that make that verification possible. We are looking for an entry-level engineer who is eager to learn technically curious and excited to work at the intersection of circuit design and CAD engineering.

In this role you will support and develop flows for two of the most critical sign-off disciplines in custom IC design transistor-level timing verification using NanoTime and formal verification using ESP. You will partner closely with analog and digital designers across multiple programs and technology nodes helping them set up flows debug issues and achieve clean sign-off. The work you do will directly shape the quality and schedule of Apples most advanced chips.

Develop maintain and improve CAD flows and automation scripts for NanoTime and ESPnSupport design teams in setting up timing and verification runs interpreting results and resolving tool and methodology issuesnDrive timing and formal verification closure in collaboration with circuit designersnContribute to methodology documentation and guidelines adopted across programs and design organizationsnEngage with EDA vendors to report issues evaluate new features and drive tool improvementsnBuild automation to improve flow efficiency reduce runtime and scale support across concurrent programs

BS degree (MS preferred) in Electrical Engineering Computer Engineering Computer Science or related fieldnProgramming or scripting experience in Perl Python TCL or similar languagenFoundational understanding of digital or custom IC design at transistor level and static timing analysis through coursework or internship experience

Exposure to tools such as NanoTime ESP PrimeTime or HSPICE is a plusnKnowledge of dynamic logic memory arrays or mixed-signal circuit techniquesnFamiliarity with SPICE netlists device models and parasitic extraction formats such as DSPF or SPFnKnowledge of formal verification tools and concepts and experience with SystemVerilog RTLnInterest in AI/ML-driven innovation for CAD workflowsnStrong communicator who can accurately describe technical issues and follow them through to resolutionnHighly motivated and able to work independently in a fast-paced environment