ASIC FPGA Design Verification Engineer – (Lead or Senior)

ASIC / FPGA Design Verification Engineer (Lead or Senior)

Company:

Boeing Space Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/ FPGA Design Verification Engineers (Lead or Senior) to join us as part of our Boeing Electronic Products team at the heart of Boeings products in El Segundo or Huntington Beach CA.

Mission

Develop scalable technical leaders who combine strong verification fundamentals fluent UVM capability technical ownership systems awareness mentorship and increasing responsibility for verification execution environments closure activities and team success.

Level Intent

Level IV engineers independently own verification scope establish verification environments and infrastructure mentor engineers support closure leadership activities and lead technical efforts when required.

Level V engineers expand into broader subsystem ownership larger technical coordination responsibilities verification strategy influence and leadership of verification efforts across complex programs.

Overview

Engineers support ASIC FPGA and SoC verification activities across advanced aerospace programs including space systems satellite technologies NASA mission support Space Launch System (SLS) technologies aviation platforms communications systems autonomous systems and related digital subsystems.

Candidates are expected to possess strong verification fundamentals and fluent UVM capability. Engineers should be prepared to discuss simulation concepts debug methods coverage approaches requirements traceability reusable verification infrastructure UVC development closure methodology and broader verification strategy concepts during interviews.

Why Join Us

This organization supports a broad portfolio of aerospace and defense programs across ASICs SoCs and FPGAs creating opportunities to contribute across multiple products technologies and technical domains over time.

Teams combine complementary technical strengths and adapt responsibilities based on program needs enabling engineers to deepen expertise while broadening systems understanding mentorship capability verification ownership and technical leadership.

The department intentionally develops scalable technical leaders and provides multiple paths for longterm growth.

Behavioral Expectations

Engineers operate with ownership appropriate to level while contributing to planning execution integration closure mentoring and continuous improvement activities. Candidates communicate status risks dependencies technical concerns and schedule impacts proactively while supporting broader team capability.

Engineers are expected to support peer growth develop broader systems awareness beyond immediate FPGA or ASIC boundaries and help strengthen verification capability across programs.

Responsibilities

Engineers independently own verification scope and contribute throughout product development by supporting verification planning requirements traceability simulation integration debug closure and delivery activities. Verification ownership includes accountability for verification execution completeness and closure. It does not imply primary ownership of architecture development RTL implementation or subsystem engineering responsibilities.

Level IV and V engineers are expected to independently establish and expand SystemVerilog and UVM environments reusable verification infrastructure and UVC development activities with minimal support while guiding broader verification execution.

Engineers are expected to define verification objectives support measurable closure criteria perform verification completeness assessments and apply metricsdriven approaches using coverage results requirements traceability bug trends and risk assessments appropriate to role level.

Responsibilities include systemlevel troubleshooting across RTL testbench firmware/software integration and specification boundaries mentoring engineers and leading technical efforts verification teams or workstreams ranging from small focused activities to larger multidiscipline efforts when needed.

This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed locations.

Basic Qualifications (Required Skills/Experience):

• This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.

• Bachelor of Science degree in Engineering (with a focus in Electrical Mechanical or Aeronautical) Computer Science Data Science Mathematics Physics Chemistry or non-US equivalent qualifications directly related to the work statement

• Bachelors degree with 9 years of professional engineering experience in ASIC FPGA or SoC design verification OR a BS/MS and 7 years of FPGA ASIC or SoC verification experience

• Strong experience with SystemVerilog for simulation testbench development and RTL debugging

• Fluent UVM experience including environment development

• 2 projects standing up verification environments and reusable infrastructure

Preferred Qualifications (Desired Skills/Experience):

• Senior Level 5: 14 years of related engineering experience

• Bachelors Degree or Masters Degree in EE Computer Engineering/Science or related field

• Active U.S. Secret Security Clearance

• 10 years of verification experience

• Strong understanding of Digital design fundamentals and systems awareness fundamentals

• Feature block subsystem or broader verification ownership

• Metricsdriven closure experience

• Requirements traceability and measurable verification objectives

• Mentoring and indirect technical leadership experience

• Project management or technical coordination experience

Conflict of Interest:

Successful candidate for this job must satisfy the Companys Conflict of Interest (COI) assessment process.

Typical Education/Experience:

Lead Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 9 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Senior (Level 5): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 14 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Relocation:

This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace:

Boeingis a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana cocaine opioids amphetamines PCP and alcohol when criteria is met as outlined in our policies.

Shift Work:

This position is for 1st shift.

Total Rewards:

At Boeing we strive to deliver a Total Rewards package that will attract engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs generally including health insurance flexible spending accounts health savings accounts retirement savings plans life and disability insurance programs and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location date of hire and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications as well as market and business considerations.

Summary pay range for Lead (Level 4): $146200 - $197800

Summary pay range for Senior (Level 5): $164900 - $223100

Language Requirements:

Not Applicable

Education:

Bachelors Degree or Equivalent

Relocation:

This position offers relocation based on candidate eligibility.

Export Control Requirement:

Safety Sensitive:

Security Clearance:

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.

Visa Sponsorship:

Employer will not sponsor applicants for employment visa status.

Contingent Upon Award Program

This position is not contingent upon program award

Shift:

Shift 1 (United States of America)

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