ASIC Design Engineering Lead SoC IP DMA
Sunnyvale, CA - USA
Job Summary
As a hands-on ASIC Design Engineering Lead you will split your time equally between leading your team and contributing directly as a technical contributor. You will:nn- Work closely with the platform architecture team to understand and refine architectural requirementsnLead your team to define and document the micro-architecturen- Provide high-level technical guidance drive micro-architectural decisions review team members work and provide feedback and ensure quality and across the teams design workn- Actively drive the development of design infrastructure automation and strategic use of AI and other emerging toolsn- Be hands-on with the all activities of the team e.g. micro-architecture RTL design verification strategy debug and infrastructure developmentn- Scope features generate effort area and power estimates and create bottoms-up project schedules and resourcing plans.n- Partner with architecture IP integration chip integration design verification and formal verification teams to align on plans milestones and deliverablesn- Track execution surface and resolve risks early and communicate clearly to management and stakeholdersn- Lead mentor and grow a team of engineers; actively invest in each persons technical and professional developmentn- Build a team culture grounded in teamwork and collaboration intellectual honesty design/idea sharing and a genuine growth mindsetn- Manage interpersonal dynamics thoughtfully and cultivate strong relationships within the team and with cross-functional teams
BS and a minimum of 20 years relevant industry experience
10 years of hands-on experience in front-end ASIC designnExperience in technical leadership: accountable for multi-person deliverables setting technical direction and interfacing effectively with management and cross-functional managing people on a team strongly desirednOutstanding written and verbal communication skills and cross-functional collaboration instinctsnExcellent project planning and execution skills: bottom-up scheduling effort area and power estimation milestone planning and execution and resource managementnSolid understanding of SoC architecture and high performance designs particularly for high speed networking AI/ML compute image and video processing and/or memory subsystems nUnderstanding of design concepts including arbitration flow control address translation caching bandwidth pipelining real time quality-of-service and AMBA protocols (AXI APB etc.).nUnderstanding of low-power design techniques including clock gating power gating and logic depth; Understanding of timing optimization and high-frequency designnTrack record of driving innovation through building tools infrastructure and automation and strategic use of emerging technologies including verification experience a plus
Required Experience:
Senior IC
About Company
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