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Description: Hybrid Austin TX (Required to work onsite every Wednesday) Laptop will be issued. Replaces ITEKJP. Please do NOT submit previously submitted candidates to JP25629 or JP25630; same sponsor VLSI Circuit Design and Physical Validation Description: The hire will be invol More...
Job Title : VLSI Circuit Design and Physical Validation Location: Austin TX Hybrid Duration: 6 months Schedule: 8am5pm MondayFriday Job Description: The hire will be involved in deep submicron IC logic and VLSI ASIC and Custom Design with Intels PROM IP for use in mobile IOT More...
Job Title ASIC Failure Analysis Engineer Relevant Experience (in Yrs) 5 years Must Have Technical/Functional Skills Bachelors in Electrical/Electronics Engineering or related required. Masters Preferred 5 years of experience in failure analysis field (preferably se More...
Must Have Technical/Functional Skills Bachelors in Electrical/Electronics Engineering or related required. Masters Preferred 5 years of experience in failure analysis field (preferably semiconductor). Semiconductor technology and process knowledge (Fab Assembly and Advanced Pac More...
ASIC Failure Analysis Engineer San Jose CA Bachelors in Electrical/Electronics Engineering or related required. Masters Preferred 5 years of experience in failure analysis field (preferably semiconductor). Semiconductor technology and process knowledge (Fab Assembly and Advan More...
Description: Hybrid Austin TX Laptop will be issued. Do not submit same candidates between JP25629 and JP25630 same sponsor. VLSI Circuit Design and Physical Validation Description: The hire will be involved in deep submicron IC logic and VLSI ASIC and Custom Design with Intels PR More...
Description: Hybrid Austin TX Laptop will be issued. Do not submit same candidates between JP25629 and JP25630 same sponsor. VLSI Circuit Design and Physical Validation Description: The hire will be involved in deep submicron IC logic and VLSI ASIC and Custom Design with Intels PR More...
AxiomaticAIs mission:AxiomaticAI is launching with the aim to accelerate R&D by Automated Interpretable Reasoning (AIR) a verifiably truthful AI model built for reasoning in science and engineering. AxiomaticAI is hiring top talent interested in a future of human reasoning aided by More...
Job Title: FPGA Design/Verification Engineer Job Duration: 06 months Contract on W2 Job Location: Littleton/Waterton CO (HYBRID). Note: US Citizen required for this position Job Description: Work with low SWaP radiation hardened space rated devices. Devise a unique veri More...
Job Description Responsibilities Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture design and verification IPs integration Understand Design for Verification concepts Drive the toplevel Architecture definition and develop the More...
Responsibilities include but not limited to: Modeling and analysis of system cache memory controller scheduling algorithms and features Develop tests testplans and testing infrastructure for new architecture/features Developing evaluating and optimizing new memory/storage architecture More...
Responsibilities include but not limited to: Modeling and analysis of system cache memory controller scheduling algorithms and features Develop tests testplans and testing infrastructure for new architecture/features Developing evaluating and optimizing new memory/storage architecture More...
Job Title: ASIC/RTL Design Engineer Senior Work Location: San Jose CA 95124 Duration: 12 Months Work Type: Contract Job Type: Hybrid Job Description: The work will expose the designer to a number of IP including ARM cores Ethernet DDR DMA PCIE SATA and clien More...
RTL Design CPU RiskV: Good to have ARM SubSystem Verilog IP Integration ASIC 7NM Good Experience guy to work on his own 78 Years exp. minimum Multiclock Domain Synthesis AXI/AMBA protocol TOP skills: RTL Soc design integration AXI LINT and CDC
THE ROLE: We are searching for a senior RTL engineer to join the PLL design team responsible for defining specifying modeling and implementing RTL for current and future advanced PLL IPs Join a dynamic team and give a boost to your personal career in a challenging and fascinating e More...
Perform presilicon validation for customer flagship silicon Liaise with design teams Communicate and coordinate with offshore teams Be the main interface for the customer EIS : ASIC Frontend Modeling RTL design and Implementation 810 PCIe (Gen 5) and NVMe experi More...
CNEX Labs Inc. is a stealth mode startup company chartered with developing hardware and software solutions for solidstatestorage. Led by an experienced management team and wellfunded by strategic investments from tier 1 companies in storage and networking CNEX is quickly advancing pro More...
Your IT Recruiter is looking for a Verification Engineer for our client.Responsible for ASIC & FPGA development on a R&D program. This engineer with have experience in developing testing and integrating FPGA platforms. Experience with COTS based control platforms and embedded More...
CNEX Labs Inc. is a stealth mode startup company chartered with developing hardware and software solutions for solidstatestorage. Led by an experienced management team and wellfunded by strategic investments from tier 1 companies in storage and networking CNEX is quickly advancing pro More...
Job Title: ASIC/RTL Design Engineer Senior Work Location: La Jolla CA 92037 Duration: 9 Months Work Type: Contract Job Type: Onsite JOB DUTIES: Knowledge/Experience Knowledge in running synthesis using Design Compiler or any equivalent tool. Knowledge of standard cell differe More...
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