Summer internship – Digital design engineer

Location: Cambridge UK
Duration: 10 to 12 weeks (Mid-June to September 2027)
Paid internship: 30k (undergrad) up to 35k (postgrad)

Please apply by 30th January 2027

Imagine the innovations we could achieve together if production-ready commercial-grade IP components and engineering systems were available to everyone for lowRISC we believe that open-source development can transform the semiconductor industry.

Our Ibex CPU and OpenTitan Root of Trust projects have been taken to production silicon partnering with world-leading organisations including Google combining open-source approaches with best practice chip design methodologies.

lowRISC is a non-profit Community Interest Company: with a business model that includes member fees and engineering services we have shown that it is possible to run world-leading projects collaboratively for everyones benefit. Originally a spinoutfrom Cambridge Universitys Computer Lab our UK team is based in Cambridge and our Switzerland team is based in Zurich.

We are looking for a Summer Intern with an interest in hardware design to support our engineering teams. This internship offers hands-on exposure to digital design and design verification through open-source projects of commercial grade quality.

You may work on:

• Digital design workflows using SystemVerilog or equivalent
• Developing testbenches and automated verification scripts using UVM or equivalent
• Analysing verification results to improve hardware reliability
• Contributing to open-source repositories and documentation

We are looking for students who:

• Are studying Computer Science Electronic Engineering or related fields 2nd year Bachelors or part way through a Masters or PhD
• Have experience or interest in digital design or design verification
• Are comfortable with a hardware description language and Python or scripting for verification
• Are curious proactive and enjoy collaborative problem solving

Bonus skills (not required):

• Familiarity with RISC-V architectures
• Knowledge of UVM / SystemVerilog testbenches

• Competitive salary 30k for undergrad and up to 35k for a postgrad
• Mentorship from engineers leading open-source hardware projects
• Flexible hybrid working environment
• Opportunity to contribute to globally used open-source projects
• Collaborative project based culture

Submit the following via our website:

• Your CV
• A short cover letter explaining your interests and experience
• Optional: Links to open-source repositories

Further questions can be sent to emailprotected

We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age disability ethnicity gender gender reassignment religion or belief sexual orientation marital or civil partnership status or pregnancy and maternity/paternity.

If you need any adjustments made to the application or selection process please let us know by emailing emailprotected