Renesas Electronics

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key ResponsibilitiesDesign package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modul

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key ResponsibilitiesDesign package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modul

Key ResponsibilitiesJob functions would include (but not limited to): Product family ownershipOwn and drive business performance (P&L revenue gross margin profitability design wins)Develop and maintain revenue demand and P&L forecastsDevelop pricing strategy and execute pricing-to-win

Key ResponsibilitiesJob functions would include (but not limited to): Product family ownershipOwn and drive business performance (P&L revenue gross margin profitability design wins)Develop and maintain revenue demand and P&L forecastsDevelop pricing strategy and execute pricing-to-win

We are seeking an experienced and strategic Director of Semiconductor IC Packaging Assembly Operations to lead high-volume semiconductor assembly operations for advanced packaging technologies. This role is accountable for converting qualified package technologies and NPI programs int

We are seeking an experienced and strategic Director of Semiconductor IC Packaging Assembly Operations to lead high-volume semiconductor assembly operations for advanced packaging technologies. This role is accountable for converting qualified package technologies and NPI programs int

Job SummaryAn NPI (New Product Introduction) Planner manages production planning scheduling and material readiness for new product launches bridging the gap between engineering design and full-scale manufacturing. Key duties include generating quarterly/weekly production plans coordin

Job SummaryAn NPI (New Product Introduction) Planner manages production planning scheduling and material readiness for new product launches bridging the gap between engineering design and full-scale manufacturing. Key duties include generating quarterly/weekly production plans coordin

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key Responsibilities Design package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modu

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key Responsibilities Design package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modu

Job Summary:We are seeking an experienced Senior Principal Engineer / Senior Manager Physical Design Lead to lead the implementation and delivery of next-generation high-performance SoC products built on advanced process technologies. This role will be responsible for driving the com

Job Summary:We are seeking an experienced Senior Principal Engineer / Senior Manager Physical Design Lead to lead the implementation and delivery of next-generation high-performance SoC products built on advanced process technologies. This role will be responsible for driving the com

Job Summary:We are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID). The candidate will be responsible for leading verification efforts across complex

Job Summary:We are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID). The candidate will be responsible for leading verification efforts across complex

Key Responsibilities:1. System & Topology Architecture Chassis & Rack Definition: Lead the structural electrical and logical design of the UALink switch chassis defining high-speed backplane topologies cabled scale-up fabrics and multi-tier switch hierarchies. Signal & Power Integrity

Key Responsibilities:1. System & Topology Architecture Chassis & Rack Definition: Lead the structural electrical and logical design of the UALink switch chassis defining high-speed backplane topologies cabled scale-up fabrics and multi-tier switch hierarchies. Signal & Power Integrity

Job Summay:As the Principal Firmware Architect for UALink Switch Products you will serve as the technical visionary responsible for defining designing and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this h

Job Summay:As the Principal Firmware Architect for UALink Switch Products you will serve as the technical visionary responsible for defining designing and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this h

Role Description The (Senior) Account Manager is responsible for driving revenue growth customer success and long-term strategic partnerships across a portfolio of assigned strategic accounts. This role acts as the primary commercial advisor to customers helping them achieve their bus

Role Description The (Senior) Account Manager is responsible for driving revenue growth customer success and long-term strategic partnerships across a portfolio of assigned strategic accounts. This role acts as the primary commercial advisor to customers helping them achieve their bus

1. System & Topology Architecture Chassis & Rack Definition: Lead the structural electrical and logical design of the UALink switch chassis defining high-speed backplane topologies cabled scale-up fabrics and multi-tier switch hierarchies. Signal & Power Integrity Collaboration: Partn

1. System & Topology Architecture Chassis & Rack Definition: Lead the structural electrical and logical design of the UALink switch chassis defining high-speed backplane topologies cabled scale-up fabrics and multi-tier switch hierarchies. Signal & Power Integrity Collaboration: Partn

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

ComponentBenchValidation andCharacterization Leveragebestknowntest and measurement techniquesincludingdeembeddinghighimpedanceprobing and noise compensationto address complexsignalintegritychallenges as memory data rates continue to scale. Support Design and Validation teams in the ch

ComponentBenchValidation andCharacterization Leveragebestknowntest and measurement techniquesincludingdeembeddinghighimpedanceprobing and noise compensationto address complexsignalintegritychallenges as memory data rates continue to scale. Support Design and Validation teams in the ch

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

1. Architectural Definition & Design Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC. Hardware-Software Co-Design: Collaborate heavily with ASIC design logic design (RTL) and verification tea

1. Architectural Definition & Design Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC. Hardware-Software Co-Design: Collaborate heavily with ASIC design logic design (RTL) and verification tea

створення проєкту тестування та відлагодження роботи мікросхем;створення технічної документації;можлива участь в розробці нових продуктів платформ та обладнання.Qualifications : вища освіта в напрямку електроніки та телекомунікацій метрології та автоматизації; (кандидати інших галузе

створення проєкту тестування та відлагодження роботи мікросхем;створення технічної документації;можлива участь в розробці нових продуктів платформ та обладнання.Qualifications : вища освіта в напрямку електроніки та телекомунікацій метрології та автоматизації; (кандидати інших галузе

募集背景自動車の電動化知能化が進む中車載SoCはクルマの性能機能を支える中核技術として位置づけられていますR-CarシリーズはCPU高速インタフェースメモリAIビデオ機能安全セキュリティなど多数の異なるSoC IPを高度に統合した大規模SoCとして発展を続けてきました当部門ではSoC製品開発における設計フロー要件管理およびトレーサビリティドキュメンテーションの管理開発およびお客様に提供するハードウェアマニュアルの作成を担っております本募集ではSoC製品開発におけるドキュメンテーション作成ワークフローの開発およびハードウェアマニュアルの開発において効率的な作成フロー

募集背景自動車の電動化知能化が進む中車載SoCはクルマの性能機能を支える中核技術として位置づけられていますR-CarシリーズはCPU高速インタフェースメモリAIビデオ機能安全セキュリティなど多数の異なるSoC IPを高度に統合した大規模SoCとして発展を続けてきました当部門ではSoC製品開発における設計フロー要件管理およびトレーサビリティドキュメンテーションの管理開発およびお客様に提供するハードウェアマニュアルの作成を担っております本募集ではSoC製品開発におけるドキュメンテーション作成ワークフローの開発およびハードウェアマニュアルの開発において効率的な作成フロー

Individual will be responsible for managing the hardware development of SOC/MCU from concept to mass production. During the life cycle of the project he would be responsible for Responsibilities:Solid technical background with understanding and/or hands-on experience in of HW Chip dev

Individual will be responsible for managing the hardware development of SOC/MCU from concept to mass production. During the life cycle of the project he would be responsible for Responsibilities:Solid technical background with understanding and/or hands-on experience in of HW Chip dev

Design and develop SW frameworks for Renesas ICs product evaluation including design definition GUI automated testing SW/HW interface and web-based technologies. Provide support to internal and external customers for SW issues system integration and evaluation.Principal Accountabiliti

Design and develop SW frameworks for Renesas ICs product evaluation including design definition GUI automated testing SW/HW interface and web-based technologies. Provide support to internal and external customers for SW issues system integration and evaluation.Principal Accountabiliti

Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive SoC planning integration strategy execution schedules risk management and tape-out readiness.Lead cross-functional teams across digital design verification phys

Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive SoC planning integration strategy execution schedules risk management and tape-out readiness.Lead cross-functional teams across digital design verification phys