Renesas Electronics

As the Principal Firmware Architect for UALink Switch Products you will serve as the technical visionary responsible for defining designing and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact

As the Principal Firmware Architect for UALink Switch Products you will serve as the technical visionary responsible for defining designing and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact

As the Principal Firmware Architect for UALink Switch Products you will serve as the technical visionary responsible for defining designing and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact

As the Principal Firmware Architect for UALink Switch Products you will serve as the technical visionary responsible for defining designing and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact

As the Senior Principal Platform Architect for UALink Switch Products you will be the ultimate system-level authority responsible for defining the end-to-end hardware software and management architecture of our next-generation AI scale-up network chassis. In this role you will look be

As the Senior Principal Platform Architect for UALink Switch Products you will be the ultimate system-level authority responsible for defining the end-to-end hardware software and management architecture of our next-generation AI scale-up network chassis. In this role you will look be

Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive SoC planning integration strategy execution schedules risk management and tape-out readiness.Lead cross-functional teams across digital design verification phys

Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive SoC planning integration strategy execution schedules risk management and tape-out readiness.Lead cross-functional teams across digital design verification phys

Our Failure Analysis Team is looking for a Senior Staff Failure Analysis Engineer in our Palm Bay Florida office with failure analysis experience in Power Management to help the growing demand and support for power requirement with Artificial Intelligence. We are seeking an enthusiast

Our Failure Analysis Team is looking for a Senior Staff Failure Analysis Engineer in our Palm Bay Florida office with failure analysis experience in Power Management to help the growing demand and support for power requirement with Artificial Intelligence. We are seeking an enthusiast

Enterprise Strategic Account Manager (Enterprise Sales)Role OverviewThe Enterprise Strategic Account Manager is responsible for driving revenue growth retention and expansion across a defined set of named enterprise accounts. This role owns the end-to-end sales lifecyclefrom executive

Enterprise Strategic Account Manager (Enterprise Sales)Role OverviewThe Enterprise Strategic Account Manager is responsible for driving revenue growth retention and expansion across a defined set of named enterprise accounts. This role owns the end-to-end sales lifecyclefrom executive

Product Strategy & Planning Define product strategy roadmap and portfolio for target markets (AI servers data centers networking telecom and computing) Conduct competitive analysis and monitor market dynamics to inform strategic positioning Develop business cases and market requiremen

Product Strategy & Planning Define product strategy roadmap and portfolio for target markets (AI servers data centers networking telecom and computing) Conduct competitive analysis and monitor market dynamics to inform strategic positioning Develop business cases and market requiremen

Lead cross-functional capacity expansion and cost reduction initiatives across product design manufacturing test packaging sourcing and operations Drive structured cost reduction programs from opportunity identification through implementation and savings realizationCoordinate activiti

Lead cross-functional capacity expansion and cost reduction initiatives across product design manufacturing test packaging sourcing and operations Drive structured cost reduction programs from opportunity identification through implementation and savings realizationCoordinate activiti

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key Responsibilities Design package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modu

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key Responsibilities Design package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modu

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key ResponsibilitiesDesign package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modul

Qualify Assembly Sustenance and Process Improvements on Power QFN package and Cu Clip related thin die assembly processes.Key ResponsibilitiesDesign package develop processes to qualify PQFN (Power Quad Flat-No lead) packages for SPS (Smart Power Stage) products & its associated modul

Individual will be responsible for managing the hardware development of SOC/MCU from concept to mass production. During the life cycle of the project he would be responsible for Responsibilities:Solid technical background with understanding and/or hands-on experience in of HW Chip dev

Individual will be responsible for managing the hardware development of SOC/MCU from concept to mass production. During the life cycle of the project he would be responsible for Responsibilities:Solid technical background with understanding and/or hands-on experience in of HW Chip dev

Design and develop SW frameworks for Renesas ICs product evaluation including design definition GUI automated testing SW/HW interface and web-based technologies. Provide support to internal and external customers for SW issues system integration and evaluation.Principal Accountabiliti

Design and develop SW frameworks for Renesas ICs product evaluation including design definition GUI automated testing SW/HW interface and web-based technologies. Provide support to internal and external customers for SW issues system integration and evaluation.Principal Accountabiliti

Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive SoC planning integration strategy execution schedules risk management and tape-out readiness.Lead cross-functional teams across digital design verification phys

Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive SoC planning integration strategy execution schedules risk management and tape-out readiness.Lead cross-functional teams across digital design verification phys

ComponentBenchValidation andCharacterization Leveragebestknowntest and measurement techniquesincludingdeembeddinghighimpedanceprobing and noise compensationto address complexsignalintegritychallenges as memory data rates continue to scale. Support Design and Validation teams in the ch

ComponentBenchValidation andCharacterization Leveragebestknowntest and measurement techniquesincludingdeembeddinghighimpedanceprobing and noise compensationto address complexsignalintegritychallenges as memory data rates continue to scale. Support Design and Validation teams in the ch

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle Park NC or the Palm Bay FL locations. The ideal candidate must have a proven track record of designing Analog and mixed signal ICs in Precision Analog and

1. Architectural Definition & Design Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC. Hardware-Software Co-Design: Collaborate heavily with ASIC design logic design (RTL) and verification tea

1. Architectural Definition & Design Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC. Hardware-Software Co-Design: Collaborate heavily with ASIC design logic design (RTL) and verification tea

1. System & Topology Architecture Chassis & Rack Definition: Lead the structural electrical and logical design of the UALink switch chassis defining high-speed backplane topologies cabled scale-up fabrics and multi-tier switch hierarchies. Signal & Power Integrity Collaboration: Partn

1. System & Topology Architecture Chassis & Rack Definition: Lead the structural electrical and logical design of the UALink switch chassis defining high-speed backplane topologies cabled scale-up fabrics and multi-tier switch hierarchies. Signal & Power Integrity Collaboration: Partn

створення проєкту тестування та відлагодження роботи мікросхем;створення технічної документації;можлива участь в розробці нових продуктів платформ та обладнання.Qualifications : вища освіта в напрямку електроніки та телекомунікацій метрології та автоматизації; (кандидати інших галузе

створення проєкту тестування та відлагодження роботи мікросхем;створення технічної документації;можлива участь в розробці нових продуктів платформ та обладнання.Qualifications : вища освіта в напрямку електроніки та телекомунікацій метрології та автоматизації; (кандидати інших галузе

募集背景自動車の電動化知能化が進む中車載SoCはクルマの性能機能を支える中核技術として位置づけられていますR-CarシリーズはCPU高速インタフェースメモリAIビデオ機能安全セキュリティなど多数の異なるSoC IPを高度に統合した大規模SoCとして発展を続けてきました当部門ではSoC製品開発における設計フロー要件管理およびトレーサビリティドキュメンテーションの管理開発およびお客様に提供するハードウェアマニュアルの作成を担っております本募集ではSoC製品開発におけるドキュメンテーション作成ワークフローの開発およびハードウェアマニュアルの開発において効率的な作成フロー

募集背景自動車の電動化知能化が進む中車載SoCはクルマの性能機能を支える中核技術として位置づけられていますR-CarシリーズはCPU高速インタフェースメモリAIビデオ機能安全セキュリティなど多数の異なるSoC IPを高度に統合した大規模SoCとして発展を続けてきました当部門ではSoC製品開発における設計フロー要件管理およびトレーサビリティドキュメンテーションの管理開発およびお客様に提供するハードウェアマニュアルの作成を担っております本募集ではSoC製品開発におけるドキュメンテーション作成ワークフローの開発およびハードウェアマニュアルの開発において効率的な作成フロー