Design Verification Lead

• BE/ME/MTech/MS in Electrical Engineering
• 6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
• 4 to 5 years of relevant industry experience for the RTL Verification Engineer position
• Proficiency in advanced verification methodologies like UVM/OVM/VMM/System Verilog
• Experience in constrained random stimulus generation assertionbased verification and functional coverage techniques.
• Knowledge of register verification standards NLP/GLS verification flows
• Strong experience in IP level and subsystem level verification on protocols such as PCIE UCIe HBM etc.
• Relevant experience in enabling and verifying controller interoperability testing at the subsystem level is a plus

• Lead a highly motivated verification team responsible for DV for IPs like UCIe HBM PCIe Bus logic etc. (Senior RTL Verification Lead)
• Implement advanced verification methodologies such as UVM/OVM/VMM/System Verilog
• Generate constrained random stimulus and perform assertionbased verification.
• Ensure functional coverage techniques are applied effectively.
• Apply register verification standards and NLP/GLS verification flows.
• Conduct IP level and subsystem level verification on protocols like PCIE UCIe HBM etc.
• Enable and verify controller interoperability testing at the subsystem level.

• 6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
• 4 to 5 years of relevant industry experience for the RTL Verification Engineer position

rtl verification,ip,verilog,universal verification methodology (uvm),vmm