DFT Engineer

Location: Santa Clara California
Duration: Long-Term Contract / Full-Time
Work Type: Onsite

We are seeking an experienced DFT Engineer with strong expertise in Design for Testability (DFT) ATPG and SoC/ASIC validation. The ideal candidate will be responsible for implementing and validating DFT architectures generating ATPG patterns supporting MBIST integration and ensuring high test coverage for complex semiconductor designs.

• Develop and implement DFT solutions for SoC/ASIC designs
• Perform scan insertion ATPG pattern generation analysis and debug
• Work on MBIST architecture integration and memory diagnostics
• Support IO Test methodologies for interface and pin-level validation
• Execute clock DFT implementation and clock verification activities
• Collaborate with RTL design verification and physical design teams
• Analyze test coverage and improve fault detection efficiency
• Debug DFT-related issues during simulation and silicon bring-up
• Ensure compliance with project quality and test requirements

• 5 years of hands-on experience in DFT and ATPG for SoC or ASIC designs
• Strong understanding of DFT fundamentals including:
  • Controllability
  • Observability
  • Scan-based testing
• Proven expertise in:
  • ATPG pattern generation
  • Pattern analysis
  • Debug and fault diagnosis
• Experience with MBIST memory test architectures and diagnostics
• Knowledge of IO Test methodologies and interface validation
• Strong understanding of clock DFT and clock verification concepts
• Solid knowledge of digital design and RTL fundamentals
• Experience with industry-standard DFT/ATPG EDA tools
• Excellent analytical debugging and problem-solving skills
• Strong communication and teamwork abilities
• Ability to work in fast-paced semiconductor development environments

• Bachelors Degree in Electronics Engineering Electrical Engineering Computer Engineering or related field