Design Verification Engineer

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry critical AI infrastructure and the broader systems that power our world in partnership with the worlds most advanced institutions. We work as one team across New York City San Francisco London Copenhagen and Pangyo.

As a Design Verification Engineer at Normal you will verify our own physics-inspired ASICs on the road to tapeout and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time you may also be tapped to support a customer deployment alongside our forward-deployed team where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise applied to silicon that computes differently than anything youve verified before and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.

• Thermodynamic ASIC Verification: Own design verification for Normals internal silicon: testbench environments assertions and coverage from design documents through functional coverage and closure supporting the program to tapeout.

• AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.

• Data Quality Bar: Set the quality standard for verification training data: define rubrics curate golden examples and partner with our Data team who own the pipelines so our models learn from verification artifacts a real DV engineer would sign off on.

• Deployment Support: When needed support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.

• Tooling: Set up and evaluate EDA tools ensuring usability and effective deployment on shared computing resources internally and in customer environments.

• 5 years of experience in digital verification at a major semiconductor or EDA tool company

• Advanced proficiency in SystemVerilog UVM methodology and EDA verification tools (vManager Xcelium Jasper) with strong Python or Perl scripting

• Proven expertise in end-to-end design verification including test plan creation stimulus generation and feature extraction

• Willingness to occasionally support customer-facing deployment work including some travel

• Excellent written and spoken communication skills: you can hold the room with a customers verification lead as credibly as you hold a debug session

• Experience in a customer-facing field-application or forward-deployed engineering role at a semiconductor or EDA company

• Hands-on use of LLMs or agentic tools in verification workflows

• Exposure to analog mixed-signal or unconventional compute verification

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation gender identity national origin disability veteran status or any other legally protected status.

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Required Experience:

IC