Principal Static Timing Analysis Engineer

PrincipalStatic Timing Analysis Engineer
Austin TX

This positioninvolves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems.These SoC devices are multi-core multi-threaded processor subsystems with multi-level cache capable of supporting multiple wireless protocols and application functionality such as sensor hub AI /MLand are specified to exceed best-in-classpower targets.These SoCs deploy a complex deeply gated clock network with many asynchronous clock sources.

Responsibilities

• Develop timing constraints at both the IP and SoC level in collaboration with the designers

• Improve or evolve existing static timinganalysisflows and methodologies.

• Developrequired timing signoff criteria such as aging on chip variationandsignal integrity

• Analyze timing reports using scripting techniques to develop insights and drive rapid timing closure

• Collaborate with a global design team to resolve complex static timing issues

• Collaborate with a multi-functional team to drive timing closure for mixed-signal IP integration
  

• 15 yearsin Industry

• BachelororMasters degree in Electrical or Computer Engineering

• In depth knowledge of the timing closure flow andmethodology

• Experience intiming constraint development both functional and test modes (such as scan)

• Hands-on experiencewith static timing tools such as Tempus or Primetime

• In depth knowledge of scripting languages like Perl PythonTcl shell

• Knowledge oftiming closuremodes and corners

• Knowledge of low power designmethodology(static/dynamic clock gating power gating dynamicvoltageand frequency scaling)

• Knowledge oftiming model generation of mixed signal IP

• Knowledge of design flows including Lint CDC SynthesisLogic Equivalence DFT Place and Route

• Knowledge of Verilog and System Verilog
  

• Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity analysis and decision-making