VP of Architecture

Position Overview

The VP of Architecture is the most senior technical individual contributor on hardware responsible for leading the endtoend chipset roadmap from concept through tapeout. This role will architect the central processor at the heart of the silicon platform design the highperformance memory fabric and collaborate closely with system software teams to ensure the hardware fully unlocks the performance of the largescale inference stack.

Key Responsibilities

Define and own the multigeneration SoC roadmap: core selection AI accelerator integration and highspeed interconnects for data centerclass workloads.

Architect the fusion processor core with workloadspecific extensions for LLM inference cache acceleration and secure cryptographic operations.

Design a scalable memory and storage fabric supporting tiered DRAM plus expandable multiterabyte memory pools for elastic cache management.

Lead microarchitecture reviews set performancepowerarea (PPA) targets and drive crossfunctional alignment across system software security and product teams.

Evaluate and select EDA tools manufacturing partners and IP vendors; manage relationships with key ecosystem partners and external design houses.

Represent the companys technical vision to large cloud and platform partners during requirementsgathering and proofofconcept engagements.

Establish architectural standards and design guidelines for the entire engineering organization.

Mentor and grow the architecture team as the company scales from founding phase through subsequent funding stages.

Required Skills & Experience

15 years in SoC architecture with at least one successful tapeout on a datacenter or AI inference chip.

Deep RISCV ISA expertise: core microarchitecture custom instruction extensions privilege levels and familiarity with the broader opensource ecosystem.

Expertlevel knowledge of modern CXLclass protocols: memory expander types coherency semantics and fabric topologies for disaggregated memory pools.

Strong DRAM/DDR5generation memory subsystem expertise: channel interleaving timing optimization and multirank/DIMM configurations.

Familiarity with neardata / inmemory processing architectures applied to cacheintensive or vector database workloads.

Outstanding communication skills; proven ability to present complex tradeoffs to executivelevel and major cloudpartner audiences.

Preferred Qualifications

Experience at semiconductor or systems companies building solutions for AI/ML or highperformance compute workloads.

Published work or patents in memory subsystem architecture coherent interconnects or AI accelerator design.

Experience collaborating with large cloud or hyperscale infrastructure teams on hardware/software codesign programs.