Senior Physical Design Manager – 3nm Chip Top 3D IC
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Job Location:
Monthly Salary:
Posted on:
10 hours ago
Vacancies:
1 Vacancy
Job Summary
Senior Physical Design Manager 3nm / Chip Top / 3D IC
2. Location Work Mode Experience Range- Location: Bangalore India
- Work Mode: Onsite
- Experience: 12 Years
Lead physical design and chip top integration for advanced-node (3nm) semiconductor programs. This role involves ownership of the full RTL-to-GDSII flow including implementation timing closure and physical verification. The position requires managing a team and working closely with cross-functional groups to deliver manufacturable designs aligned with performance and power targets.
4. Key Responsibilities- Lead block-level and full-chip physical design for advanced-node ASICs
- Drive chip top-level integration assembly and implementation
- Manage end-to-end physical design flow from RTL to GDSII
- Oversee floorplanning placement CTS routing and timing closure
- Ensure convergence of PPA (Power Performance Area) targets
- Perform and review physical verification (DRC LVS ERC)
- Handle parasitic extraction and timing/signoff analysis
- Drive signal integrity IR drop and EM analysis
- Implement and optimize design methodologies and flows
- Collaborate with front-end packaging and fabrication teams
- Support advanced packaging chiplet and 3D IC integration efforts
- Mentor and manage a team of physical design engineers
- Bachelors or Masters degree in Electronics / VLSI / Microelectronics
- 12 years of experience in physical design and implementation
- Proven experience in advanced node tape-outs (5nm / 3nm preferred)
- Experience managing teams and leading complex chip programs
- Strong understanding of semiconductor manufacturing and design flows
Physical Design & Implementation:
- RTL to GDSII flow
- Floorplanning placement CTS routing
- Timing closure and signoff
Verification & Signoff:
- DRC LVS ERC
- Parasitic extraction (RC extraction)
- Static Timing Analysis (STA)
Advanced Node Expertise:
- 3nm / 5nm process technologies
- Low-power design techniques
- Signal integrity IR drop electromigration
3D IC & Packaging:
- 3D IC integration
- Chiplet architecture
- Die-to-die interconnect advanced packaging
EDA Tools:
- Cadence Innovus
- Synopsys ICC2 / Fusion Compiler
- Mentor Graphics Calibre
Scripting & Automation:
- Tcl Perl Python
