Senior ASIC-FPGA Verification Engineer

Company:

Overview

As a leading global aerospace company Boeing develops manufactures and services commercial airplanes defense products and space systems for customers in more than 150 countries. As a top U.S. exporter the company leverages the talents of a global supplier base to advance economic opportunity sustainability and community impact. Boeings team is committed to innovating for the future leading with sustainability and cultivating a culture based on the companys core values of safety quality and integrity.

Technology for today and tomorrow

The Boeing India Engineering & Technology Center (BIETC) is a 5500 engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D innovation and high-quality engineering work in global markets and leverage new-age technologies such as AI/ML IIoT Cloud Model-Based Engineering and Additive Manufacturing shaping the future of aerospace.

People-driven culture

At Boeing we believe creativity and innovation thrives when every employee is trusted empowered and has the flexibility to choose grow learn and explore. We offer variable arrangements depending upon business and customer needs and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration frequent team engagements and face-to-face meetings bring together different perspectives and thoughts enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work we are committed to positively shaping peoples careers and being thoughtful about employee wellbeing.

With us you can create and contribute to what matters most in your career community country and world. Join us in powering the progress of global aerospace.

Position Overview

Boeing India Engineering seeks a Senior ASIC-FPGAVerification Engineer with considerable experience in designto support multiple product lines in commercial and defense electronics development.

Primary Responsibilities:

• Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and test plan using UVM for IP Subsystem and System level verification.
• Develop reusable testbench components like scoreboards checkers reference models along with UVC using SV and UVM
• Own quality of deliverables for verification across multiple milestones for FPGA/ASIC life cycle
• Architect Reusable Verification components which can be used across FPGA/ASIC life cycle
• Lead drive and collaborate technical reviews with Validation Design and System Architecture cross functional teams.
• Support Architecture exploration at system level using System C or TLM models using SV-UVM
• Verification Domain expert for PCIe and Ethernet protocols
• Identifies tracks and status technical performance measures to measure progress and ensure compliance with verification requirements.
• Develop Junior engineers solve simple to complex technical problems in verification
• Support in Technical strategy in collaboration with Engineering management for the FPGA/ASIC V&V.
• Should lead AI initiatives for Verification Automation and Verification Reviews

Basic Qualifications (Required Skills/Experience):

• Bachelor degree in Engineering Engineering Technology (including Manufacturing Technology Micro Electronics VLSI/CAD/Embedded systems) Computer Science Data Science Mathematics Physics Chemistry or non-US equivalent qualifications directly related to the work statement.
• 13to 17 years of experience in Digital Functional verification for both ASIC and FPGA at IP Subsystem and System level as a Lead or Verification Architect.
• 8 years of experience in leading and owning verification Activities for Multiple ASIC and FPGA product Tape outs.
• 7 years of experience in Developing and mentoring Verification engineers
• 5 years of Hands-on domain experience on PCIe (Transaction layer) and Ethernet (Mac Layer)
• Multiple Verification tape out experience in ASIC and FPGA products
• 5 years of experience in doing UVM based Testbench Architecture for PCIe and Ethernet across IP/Subsystem and system level for multiple projects in ASIC and FPGA

Preferred Qualifications (Desired Skills/Experience):

• Experience in leading Verification team for complex Ip Subsystem and system along with Verification Architecture for ASIC and FPGA Products.
• Experience identifying tracking and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
• Experience directing a team of engineers for technical excellence.
• Expert in using object-oriented programing in System Verilog along with UVM methodology.
• Expert in using Universal Verification Methodology (UVM): Experience crafting drivers monitors predictors coverage model and scoreboards and UVCs.
• Expertise in verification working with internal/external VIPs its development and evaluation with multiple vendors.
• Expert in crafting SVA -Assertions for dynamic simulation and formal verification
• Expert in coverage (code and functional) signoff by reviewing complex ASIC and FPGA RTL code.
• Work experience using Linux or Unix terminal commands.
• Experience using scripting languages: Make Perl Python shell scripts etc.
• Experience using Revision Control Systems: Subversion (SVN) CVS Git.
• Experience in deriving digital ASIC and FPGA verification requirements specification from higher-level (system or board-level) requirements specifications.
• Experience in Power aware simulation debug with along Gate level simulation debug
• Experience in Avionics protocols is a plus.
• Experience in DO -254 for ASIC /FPGA is a plus

Typical Education & Experience:

Bachelor Master degree In Electronics Engineering Electrical Engineering with 17 to 20years of experience & Masters degree with 16 years of experience.

Relocation:

This position offers relocation based on candidate eligibility.

Language Requirements:

Education:

Relocation:

Security Clearance:

Visa Sponsorship:

Contingent Upon Award Program

Shift: