Lead PD Engineer

Bengaluru - India

Monthly Salary: Not Disclosed

Posted on: Yesterday

Vacancies: 1 Vacancy

Job Summary

Job Summary:

The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floor planning Placement CTS routing timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules such as DRC/LVS/Electromigration/IR drops. The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.

Experience
Self-Starter with at-least 8 years of relevant experience P&R Good knowledge on STA Physical Verification and EMIR.

Job Responsibilities

* Execute physical design activities including floorplanning power planning place and route clock tree synthesis and static timing analysis (STA).
* Perform physical verification (DRC LVS Antenna) and resolve related issues.
* Conduct power integrity analysis (IR drop EM) and optimize designs for power efficiency.
* Participate in design-for-test (DFT) implementation and verify test structures.
* Collaborate with design verification and DFT teams to ensure seamless integration and achieve project milestones.
* Analyze and resolve design issues related to timing area and power.
* Develop and maintain scripts for automation and efficiency improvements in the physical design flow.
* Contribute to the continuous improvement of physical design methodologies and flows.
* Generate comprehensive reports and documentation of design implementation.

Job Qualifications

* Bachelors or Masters degree in Electronics Engineering or a related field.
* Minimum 7 years of experience in digital physical design of complex SoCs or ASICs.
* Proficiency with industry-standard EDA tools for physical design (e.g. Innovus Cadence Genus/Tempus/Voltus/Pegasus Mentor Calibre Apache Redhawk).
* Solid understanding and experience of physical design concepts including floorplanning placement routing clock tree synthesis and physical verification.
* Strong knowledge of Static Timing Analysis (STA) and timing closure techniques.
* Experience with scripting languages such as Tcl Perl or Python.
* Familiarity with deep sub-micron process technologies.
* Good understanding of VLSI design principles and semiconductor physics.
* Excellent problem-solving skills and attention to detail.
* Ability to work effectively in a collaborative team environment.
* Good communication skills both written and verbal.

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Required Experience:

Job Summary:The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floor planning Placement CTS routing timing convergence ...

Job Summary:

Experience
Self-Starter with at-least 8 years of relevant experience P&R Good knowledge on STA Physical Verification and EMIR.

Job Responsibilities

* Execute physical design activities including floorplanning power planning place and route clock tree synthesis and static timing analysis (STA).
* Perform physical verification (DRC LVS Antenna) and resolve related issues.
* Conduct power integrity analysis (IR drop EM) and optimize designs for power efficiency.
* Participate in design-for-test (DFT) implementation and verify test structures.
* Collaborate with design verification and DFT teams to ensure seamless integration and achieve project milestones.
* Analyze and resolve design issues related to timing area and power.
* Develop and maintain scripts for automation and efficiency improvements in the physical design flow.
* Contribute to the continuous improvement of physical design methodologies and flows.
* Generate comprehensive reports and documentation of design implementation.

Job Qualifications

* Bachelors or Masters degree in Electronics Engineering or a related field.
* Minimum 7 years of experience in digital physical design of complex SoCs or ASICs.
* Proficiency with industry-standard EDA tools for physical design (e.g. Innovus Cadence Genus/Tempus/Voltus/Pegasus Mentor Calibre Apache Redhawk).
* Solid understanding and experience of physical design concepts including floorplanning placement routing clock tree synthesis and physical verification.
* Strong knowledge of Static Timing Analysis (STA) and timing closure techniques.
* Experience with scripting languages such as Tcl Perl or Python.
* Familiarity with deep sub-micron process technologies.
* Good understanding of VLSI design principles and semiconductor physics.
* Excellent problem-solving skills and attention to detail.
* Ability to work effectively in a collaborative team environment.
* Good communication skills both written and verbal.