1. Strong academic background in Electrical Engineering (Bachelors required Masters preferred)
2. 7-10 years of pure verification experience in ASIC/FPGAs
3. Experience with PCIe Ethernet slow speed interfaces like I2C SPI MDIO etc and developing object-oriented testbench infrastructure BFMs and testcases in UVM.
4. Ability to independently develop test plans test sequences generate stimuli and collaborate with RTL designers to debug failures.
1. Strong academic background in Electrical Engineering (Bachelors required Masters preferred) 2. 7-10 years of pure verification experience in ASIC/FPGAs 3. Experience with PCIe Ethernet slow speed interfaces like I2C SPI MDIO etc and developing object-oriented testbench infrastructure BFMs and tes...
1. Strong academic background in Electrical Engineering (Bachelors required Masters preferred)
2. 7-10 years of pure verification experience in ASIC/FPGAs
3. Experience with PCIe Ethernet slow speed interfaces like I2C SPI MDIO etc and developing object-oriented testbench infrastructure BFMs and testcases in UVM.
4. Ability to independently develop test plans test sequences generate stimuli and collaborate with RTL designers to debug failures.
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