Sr StaffStaffSenior Engineer– IP Design Verification
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Monthly Salary:
Posted on:
17 hours ago
Vacancies:
1 Vacancy
Job Summary
Renesas has a growing presence in India with HC approaching 1000 and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub our divisions (India for India) mission is to grow India market. We aspire to create products (SoCs Software Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new fast growing and large Indian market with specific needs and applications.
We are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D this role you will be a part of team responsible for SOC verification ensuring firstpass silicon success through building verification environment from scratch using best in class methodologies metricdriven verification and intelligent coverage convergence using AI tools.
You will play a key technical role in defining verification strategies architecting testbenches defining Test Plans tracing Requirements driving coverage closure using advanced automation and AIassisted techniques and collaborating closely with Architecture RTL chip top and Validation teams to deliver highquality reusable IPs for nextgeneration microcontrollers and microprocessors.
Responsibilities:
- Be a part of endtoend verification execution for SOC owning complex digital IPs and subsystems from specification to signoff
- Define and drive IPlevel verification strategies including test plans coverage models and closure criteria
- Develop scalable reusable UVMbased verification environments for IP and subsystem verification
- Lead functional code assertion and crosscoverage closure ensuring highquality signoff with clear metrics
- Apply AI/MLassisted verification techniques to accelerate coverage convergence identify stimulus gaps and optimize regression efficiency
- Drive constraint random and directed test methodologies for thorough protocol cornercase and stress verification
- Collaborate with RTL Architecture Emulation and SoC Verification teams to ensure seamless IP integration
- Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
- Develop and deploy advanced checkers scoreboards assertions (SVA) and protocol monitors
- Work with EDA vendors to evaluate and adopt nextgeneration verification coverage and analytics tools
- Mentor junior engineers and promote bestinclass verification practices and continuous improvement
- Support GateLevel Simulation (GLS) lowpower verification and postsilicon debug when required.
- Ensure IP deliverables meet quality schedule and reusability expectations for SoC integration.
Qualifications :
- Bachelors or Masters degree in electronics Engineering
- 5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
- Strong expertise in UVMbased testbench architecture and development
- Proven experience in metricdriven verification including functional and code coverage closure
- Deep understanding of SystemVerilog UVM assertions (SVA) and verification best practices
- Experience with directed and constrainedrandom verification methodologies
- Experience debugging complex design issues in simulation emulation and postsilicon environments
- Proficiency in Verilog/SystemVerilog with working knowledge of C/C Shell scripting
- Strong analytical problemsolving and communication skills
Preferred/Plus Qualifications
- Handson experience using AI/MLbased verification tools for:
- Coverage gap analysis
- Test stimulus optimization
- Regression triage and coverage acceleration
- Scripting expertise in Python Perl or TCL for automation and analytics
- Exposure to formal verification and hybrid formalsimulation flows
- Familiarity with highspeed or complex IPs such as:
- H.264
- Security debug or safetycrititical
Additional Information :
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. As the industrys leading expert in embedded processing with unmatched quality and system-level know-how we have evolved to provide scalable and comprehensive semiconductor solutions for automotive industrial infrastructure and IoT industries based on the broadest product portfolio including High Performance Computing Embedded Processing Analog & Connectivity and Power.
With a diverse team of over 21000 professionals in more than 30 countries we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable power-efficient solutions today that help people and communities thrive tomorrow To Make Our Lives Easier.
At Renesas you can:
- Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
- Make a real impact by developing innovative products and solutions to meet our global customers evolving needs and help make peoples lives easier safe and secure.
- Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system including the remote work option and Employee Resource Groups will help you excel from the first day.
Are you ready to own your success and make your mark
Join Renesas. Lets Shape the Future together.
Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.
We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation collaboration and continuous learning.
Remote Work :
No
Employment Type :
Full-time
Key Skills
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