Mixed-Signal Design Verification Engineer | Custom

We are seeking a talented Mixed-Signal Design Verification Engineer with experience in verifying high-speed wireline communications and clock/data paths. Come be a part of an exciting Top-Level Design Verification (TLDV) Team in the ACS product line which develops cutting-edge ASSP ICs. The TLDV team builds automated AMS and DMS testbenches to verify logical functionality electrical parameters performance and reliability of custom high-volume chips. While doing that we strive for continuous improvement in our tools and methodologies and believe in teamwork and having fun.

This individual will:

• Execute the pre-silicon verification of complex mixed-signal IC products. Build testbench and automation solutions that are scalable and that support DMS and AMS stimulus and checkers to verify DUT behavior before tapeout.
• Verify high-speed clock and data paths (clock/data recovery timing serialization/de-serialization PLLs DLLs) such as USB eUSB SerDes and other wireline protocols.
• Verify the design to work according to the datasheet VVCM system-level use cases design-for-test features and usability from a customer and bench/ATE perspective.
• Work with the design teams and systems teams to provide guidance on Design for Verification architecture during chip development to triage and close bugs as they arise and to elaborate and clarify the datasheet and VVCM specifications.
• Be knowledgeable and efficient at using the languages and tools of the trade such as: Verilog SystemVerilog Verilog-AMS Cadence Virtuoso Spectre Simvision text editors scripting languages Starfish CDDS functional coverage RTL code coverage and constrained-random stimulus.
• Evaluate system-level use-cases and re-create these in simulation including communication with the customer to understand these system cases and to review results with them.
• Create and maintain behavioral models of analog circuits (real-number models simple logical models Verilog-AMS electrical or wreal models or simple schematic models).

Minimum requirements:

• 8 years of experience as a Design Verification Engineer including 4 years of design verification of high-speed clock/data paths (e.g. USB SerDes PLL DLL etc.)
• Strong understanding of mixed-signal and digital verification flows (AMS / DMS / TLDV / DDV) and modeling of analog blocks.
• Solid analog design knowledge with capability to understand and explain operation at schematic-level and awareness of the effects of PVT and layout parasitics.
• Solid digital design knowledge with capability to understand RTL FSMs GLS timing synchronization power domains and clock domains.
• Experience in verification of timing with GatesSDF electrical PVT variation and timing across analog and digital boundaries.
• Experience creating and maintaining tools and scripts for automation related to design verification simulation data collection and analysis.28
• Excellent debug skills with high attention-to-detail for both analog and digital behaviors.
• Strong leadership communication cross-team collaboration skills and customer-facing skills.
• Strong analytical and problem-solving skills.
• Ability to work in a fast-paced and rapidly-changing environment.

Preferred qualifications:

• Experience verifying USB protocol (USB2.0 and eUSB high-speed and full-speed logical and electrical)
• Experience in modeling analog blocks as real-number models using SystemVerilog EEnet
• Experience verifying re-timers re-drivers SerDes
• Experience with Verification IPs (VIPs) for USB eUSB PLLs or other SerDes interfaces