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Microns HighBandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of highperformance lowpower digital logic used in advanced memory products. This role spans backend implementation from Netlist to GDSII with a strong focus on timing closure power integrity and manufacturability in advanced process technologies. The successful candidate will work closely with RTL DFT CAD and verification teams to deliver highquality physical designs contribute to methodology improvements and help push performance power and area (PPA) targets in complex multihierarchy designs.
Key Responsibilities:
Own and execute physical design implementation from synthesized netlist through GDSII including floorplanning placement clock tree synthesis routing and physical signoff
Perform and drive timing closure across multiple modes corners and scenarios using industrystandard STA tools
Analyze and resolve congestion timing IR drop EM and power integrity issues
Develop and refine floorplans power grids and clocking strategies for highperformance designs
Work with placement and timing closure of custom analog hard IP macros in a digital-on-top design flow
Collaborate closely with RTL designers to influence partitioning constraints and microarchitecture decisions early in the design cycle
Implement and validate lowpower design techniques including multiple/isolated power domains power gating and UPF/CPFbased power intent
Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows
Drive functional and timing ECOs as needed to meet design targets
Use scripting and automation (TCL Python etc.) to improve productivity quality and flow robustness
Interface with EDA vendors and internal CAD teams to debug tool issues evaluate new tools and functions and improve physical design methodologies.
Required Qualifications
Strong understanding of the RTLtoGDSII physical design flow particularly floorplanning place & route clock distribution and timing analysis and closure using standard EDA tools and advanced process technologies
Experience with fullchip integration partitioning and budgeting
Solid understanding of power performance and area tradeoffs
Knowledge of lowpower architectures including DVFS power gating and multivoltage designs
Proficiency in scripting/programming (TCL Python Perl Shell scripting)
Strong problemsolving skills and ability to debug complex physical design issues
Effective communication skills and ability to work in a crossfunctional team environment
Experience in validating Power Distribution Network (PDN) IR/EM
Preferred Qualifications:
Experience with advanced technology nodes
Experience with highfrequency highdensity designs and complex clocking schemes
Familiarity with memory HBM or datapathintensive designs
Understanding of device physics and processtechnology impacts
Experience in the 3D-IC technology methodology and advanced packaging and thermal considerations
Education and Experience:
Required: Bachelors degree in EE with good understanding of computer architecture and 7 years experience in related field
Desired: Masters degree in EE / CE with 10 years experience in related field
As a world leader in the semiconductor industry Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well provide peace of mind and help you prepare for the future. We offer a choice of medical dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury and paid family leave. Additionally Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available please see the Benefits Guide posted on is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation age national origin citizenship status disability protected veteran status gender identity or any other factor protected by applicable federal state or local laws.
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Required Experience:
Staff IC
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