Job Position : FPGA Design/Verification Engineer
Location : Littleton CO (fully Onsite)
Duration: 09 Months (Possibility of extension/Conversion to FTE based upon performance)
Pay rate: $140/hr. on W2
Job Description:
The selected candidate will be responsible for ASIC prototyping on a R&D program.
Key activities you will accomplish in this role:
Architect and implement ASIC prototyping solutions using industry standard platforms including Synopsys HAPS
Map ASIC RTL to emulation and FPGA-based platforms
Develop and execute validation plans for complex ASIC and FPGA designs
Validate and qualify ASIC and FPGA designs through simulation hardware emulation and lab bring up
This engineer with have experience in developing ASIC prototypes on FPGA platforms like Synopsys HAPS system. This person will have:
Detailed understanding of the FPGA implementation flow
- Ability to develop test plans for an ASIC prototype
- Excellent hardware debugging skills
- Strong understanding of data streaming and packet-based protocols like ethernet UCIe and JESD204
- Ability to automate and develop scripts for the implementation and testing flows
- Collaborate with Systems Architects RTL designers ASIC verifiers and Software developers to create a representative platform for the ASIC
- Provide support and technical direction to junior engineers
- Create thorough documentation of the prototyping implementation and test flows
Prior experience with ASIC Prototyping emulation platforms is a requirement. (Synopsys HAPS/Zebu Cadence Palladium/Protium Siemens Veloce/Strato etc) - Synopsys HAPS experience preferred
Job Position : FPGA Design/Verification Engineer Location : Littleton CO (fully Onsite) Duration: 09 Months (Possibility of extension/Conversion to FTE based upon performance) Pay rate: $140/hr. on W2 Job Description: The selected candidate will be responsible for ASIC prototyping on a R&D program....
Job Position : FPGA Design/Verification Engineer
Location : Littleton CO (fully Onsite)
Duration: 09 Months (Possibility of extension/Conversion to FTE based upon performance)
Pay rate: $140/hr. on W2
Job Description:
The selected candidate will be responsible for ASIC prototyping on a R&D program.
Key activities you will accomplish in this role:
Architect and implement ASIC prototyping solutions using industry standard platforms including Synopsys HAPS
Map ASIC RTL to emulation and FPGA-based platforms
Develop and execute validation plans for complex ASIC and FPGA designs
Validate and qualify ASIC and FPGA designs through simulation hardware emulation and lab bring up
This engineer with have experience in developing ASIC prototypes on FPGA platforms like Synopsys HAPS system. This person will have:
Detailed understanding of the FPGA implementation flow
- Ability to develop test plans for an ASIC prototype
- Excellent hardware debugging skills
- Strong understanding of data streaming and packet-based protocols like ethernet UCIe and JESD204
- Ability to automate and develop scripts for the implementation and testing flows
- Collaborate with Systems Architects RTL designers ASIC verifiers and Software developers to create a representative platform for the ASIC
- Provide support and technical direction to junior engineers
- Create thorough documentation of the prototyping implementation and test flows
Prior experience with ASIC Prototyping emulation platforms is a requirement. (Synopsys HAPS/Zebu Cadence Palladium/Protium Siemens Veloce/Strato etc) - Synopsys HAPS experience preferred
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