RTL Design Engineer – DDR

Location: Bangalore
Experience: 5 Years
Education: Bachelors degree in Electrical / Electronics Engineering

We are looking for an RTL Design Engineer with strong hands-on experience in DDR-related digital design and RTL development. The role involves micro-architecture understanding RTL coding design implementation and close collaboration with verification synthesis and physical design teams for high-quality IP/SoC development.

The ideal candidate should have solid expertise in Verilog/SystemVerilog-based RTL design good understanding of DDR protocols and controller/interface design and experience in working through the full design cycle from specification to RTL delivery.

• Develop and maintain RTL design for DDR-related blocks controllers or interface logic.

• Translate architectural and functional requirements into clean synthesizable RTL.

• Work on micro-architecture definition and block-level design implementation.

• Participate in design reviews code reviews and technical discussions with cross-functional teams.

• Collaborate with verification teams to support testbench bring-up debugging and issue resolution.

• Work with synthesis and physical design teams to ensure timing-aware and implementation-friendly RTL.

• Analyze design issues debug functional mismatches and support closure of RTL/design bugs.

• Ensure compliance with coding guidelines design quality standards and project milestones.

• Support integration of DDR blocks into larger subsystem or SoC environments.

• Contribute to design documentation including functional specs interface definitions and RTL implementation notes.

• 5 years of experience in RTL design / digital design.

• Strong hands-on experience in Verilog/SystemVerilog RTL coding.

• Good understanding of DDR memory architecture and protocols.

• Experience in designing DDR controller / PHY interface related digital logic.

• Strong understanding of digital design fundamentals including FSMs pipelines clocking resets arbitration and data path design.

• Experience in block-level RTL development debugging and integration.

• Familiarity with lint CDC synthesis and static checks.

• Ability to work closely with verification architecture and backend teams.

• Good understanding of timing performance power and area trade-offs in RTL design.

• Exposure to SoC integration flows and design methodology.

• Experience with DDR4 / DDR5 / LPDDR4 / LPDDR5 related design environments.

• Familiarity with AMBA protocols such as AXI/AHB/APB.

• Exposure to low-power design concepts and reset/clock domain handling.

• Experience in working with synthesis constraints and RTL signoff checks.

• Knowledge of script-based automation using Perl / Python / Tcl is an advantage.

• RTL Design

• Verilog

• SystemVerilog

• DDR

• DDR Controller

• Digital Design

• Micro-architecture

• SoC Design

• Lint / CDC

• Synthesis Awareness

• Bachelors degree in Electrical Engineering / Electronics Engineering

• Equivalent relevant semiconductor design experience will also be considered based on technical fit

The ideal candidate should be a hands-on RTL designer with strong DDR design understanding good debugging capability and the ability to work across architecture verification and implementation teams in a structured product development environment.