Engineer II CAD

Are you looking for a unique opportunity to be a part of something great Want to join a 17000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust empowerment respect diversity and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development values-based decision making and strong sense of community driven by our Vision Mission and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

You will be part of the team that develops FPGA and FPGA SOC products which will be used in leading electronic systems. You will be involved in setting up maintaining and debugging the Cadence custom design environment. This includes making customizations to foundry PDK writing new Cadence PCells DRC/LVS rules scripting (SKILL Perl Python) and customizing Cadence netlisting environment and installing/configuring relevant EDA tools. You need to be familiar with Cadence Database organization and structure. You will participate in the architecture organization and development of new CAD flows. You will work closely with silicon design engineers technology development engineers and foundries to understand construction of new devices.

• Setting up Cadence Virtuoso full-custom design environment
• Understanding of 14nm and below FinFet process technologies.
• Pcell creation debugging and migration flows.
• Writing DRC/LVS rules using Calibre svrf.
• Work with CDL hspiceD and Verilog netlisting customizations.
• Design automation using SKILL/Perl/Python/Shell scripting
• Interface with cross-functional teams on various CAD requests.
• Good communication skills a key requirement for coordinating tasks across all different sites in different time zones

Requirements/Qualifications:

• BSEE or MSEE and 3 years of relevant work experience.
• Very good understanding of CMOS concepts and electronic fundamentals.
• Work experience in semiconductor industry especially EDA segment & CAD
• Good understanding of Cadence custom IC Virtuoso platform Virtuoso-L and Virtuoso-XL schematic capture and layout concepts.
• Basic understanding of PNR(RTL-to-GDSII) flows.
• Experience with working with foundries and PDK.
• Good understanding of Physical verification including DRC/LVS/Parasitic Extraction
• Willingness to gain knowledge and familiarity with several EDA CAD tools
• Comfortable in working in a fast paced dynamic environment with changing priorities

Travel Time:

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.