Senior Lead Microarchitecture RTL Engineer

Our client is expanding their RTL team and is looking for experienced Senior and Lead RTL Engineers with a strong background in RTL design and microarchitecture ideally within RISC V based processor development.

In this role you will contribute to the design and implementation of advanced processor components at RTL level for cutting edge technology nodes. Focus areas include the processor pipeline d cache i cache L2 pipeline and custom memory controller blocks. The team values engineers who understand architectural challenges end to end and can translate them into robust RTL implementations.

Location: Barcelona Spain - Hybrid

Responsibilities:

As a Senior / Lead Microarchitecture / RTL Engineer your broad responsibilities will include but are not limited to:

• Design and implement RTL modules in Verilog based on architectural and microarchitecture specifications

• Contribute to processor pipeline development including d cache i cache L2 pipeline and custom memory controller components

• Translate architecture concepts into efficient and scalable RTL designs

• Collaborate closely with architecture verification and physical design teams

• Develop and use scripts to support design automation and integration tasks

• Participate in design reviews and contribute to technical discussions

Additional Responsibilities for Lead RTL Engineers Only:

• Provide technical leadership within the RTL team

• Drive microarchitecture definition and key design decisions

• Mentor and guide junior and senior RTL engineers

• Coordinate work across multiple functional blocks and ensure alignment with project milestones

• Interface with cross functional leads to ensure design quality and delivery

Requirements:

• Minimum Bachelor degree in Computer Science Computer Engineering or related field

• 8 years of relevant industrial experience in RTL or microarchitecture roles

• English level C1 or higher

• Strong knowledge of Verilog

• Experience with scripting for automation and design support

Additional Requirements for Lead RTL Engineers Only:

• Proven experience leading RTL design efforts or small engineering teams

• Strong background in processor microarchitecture and system level understanding

• Demonstrated ability to take ownership of complex design blocks from concept to RTL implementation

• Excellent leadership communication and coordination skills

Whats in it for you

Our client offers an exciting challenging role in a collaborative dynamic environment. The right person will find many career growth opportunities in their company whether you want to advance your technical skills or aspire to leadership in the future.

Benefits:

• Flexible working hours ( You can work between 7 AM and 7 PM )

• Hybrid model one day remote per week

• One week per year work from anywhere

• 25 days annual leave plus additional December 24 and 31

• Private medical insurance

• Relocation package including flight visa support first month accommodation

• Relocation support for family

• Virtual shares

• Spanish language classes