PCIe Verification Engineer
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Job Location:
Silver Lake, OH - USA
Monthly Salary:
Not Disclosed
Posted on:
4 hours ago
Vacancies:
1 Vacancy
Job Summary
Role: PCIe Verification Engineer
Position Type: Contract
Location: San Jose CA Or Silver Lake CA ( Day One Onsite)
Job Description:
Experience: 7 Years Education: Bachelor/Master of Engineering (B.E./ in Electronics Electrical Computer Engineering or a related field
Role Summary:
Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4 Gen5 and Gen6 specifications. Utilizing SystemVerilog and UVM you will ensure robust protocol compliance high-performance throughput and seamless interoperability for cutting-edge silicon.
Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4 Gen5 and Gen6 specifications. Utilizing SystemVerilog and UVM you will ensure robust protocol compliance high-performance throughput and seamless interoperability for cutting-edge silicon.
Key Responsibilities:
Strategic Planning: Architect and execute comprehensive PCIe verification plans to ensure full specification coverage.
Strategic Planning: Architect and execute comprehensive PCIe verification plans to ensure full specification coverage.
Environment Development: Build and maintain sophisticated UVM-based verification environments from the ground up.
Protocol Deep-Dive: Verify intricate PCIe protocol behaviors including LTSSM transitions link training flows and complex error handling mechanisms.
Feature Validation: Validate specialized Switch and Retimer features alongside cross-vendor interoperability.
RTL Debugging: Perform rigorous debug of RTL and protocol-level issues while conducting detailed functional and code coverage analysis.
Required Skills:
Protocol Expertise: Strong command of PCIe protocols specifically Gen4 and Gen5 with Gen6 knowledge considered a significant advantage.
Protocol Expertise: Strong command of PCIe protocols specifically Gen4 and Gen5 with Gen6 knowledge considered a significant advantage.
Methodology: Advanced proficiency in SystemVerilog UVM and the implementation of functional assertions.
Tooling: Extensive experience navigating industry-standard simulators such as VCS Questa or Xcelium.
Nice to Have:
Compliance & Physical Layer: Familiarity with PCI-SIG compliance testing SerDes/Signal Integrity (SI) fundamentals and hardware emulation environments.
Compliance & Physical Layer: Familiarity with PCI-SIG compliance testing SerDes/Signal Integrity (SI) fundamentals and hardware emulation environments.
Key Skills
- Account Management
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- Jpa
- ABAP
- Community Support
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