SoC Design Lead Engineer – ASIC SoC (ARM-Based Platforms)

Experience: 10 15 Years
Location: Bengaluru India
Employment Type: Full-time

B.E./ or M.E./ in Electronics Electrical Computer Engineering or a related field.

We are seeking an accomplished SoC Design Lead Engineer to provide technical ownership and leadership for complex ARM-based SoC programs at Azimuth AI.

This role demands deep expertise in ARM architecture Arm Corestone reference systems and front-end ASIC design along with proven experience leading subsystem and SoC-level execution from architecture definition through silicon bring-up.

As a Design Lead you will drive micro-architecture decisions RTL quality integration strategy and execution excellence while mentoring engineers and collaborating closely with architecture verification physical design DFT and silicon validation teams to deliver production-ready high-performance SoCs.

• Own end-to-end design leadership for ARM-based SoC and subsystem development

• Lead the integration of Arm Corestone reference subsystems into custom SoC architectures

• Drive micro-architecture definition design trade-offs and performance optimization

• Provide technical direction on AMBA interconnects CPU subsystems memory architecture and peripheral IP integration

• Review guide and approve RTL architecture and implementation (Verilog/SystemVerilog)

• Ensure high-quality front-end design practices across lint CDC/RDC synthesis and STA readiness

• Work closely with physical design teams on timing closure power optimization and design convergence

• Lead resolution of complex cross-domain timing and functional issues

• Act as the primary technical interface between architecture verification PD DFT and validation teams

• Drive coverage closure strategy in partnership with verification leads

• Support emulation FPGA prototyping early silicon bring-up and post-silicon debug

• Lead design reviews sign-off readiness and technical risk assessments

• Establish and improve design methodologies reuse frameworks and scalable integration practices

• Mentor and technically guide junior and senior design engineers fostering design excellence

• Own technical documentation design specifications and executive-level technical communication

• Bachelors or Masters degree in Electronics Electrical or Computer Engineering

• 10 15 years of hands-on experience in ASIC SoC and subsystem design

• Strong expertise in ARM architecture and AMBA protocols (AXI AHB APB)

• Proven experience working with Arm Corestone reference systems or equivalent ARM platforms

• Deep knowledge of ASIC front-end design flows and RTL integration methodologies

• Hands-on experience with Static Timing Analysis (PrimeTime / Cadence tools)

• Strong command of CDC/RDC lint synthesis and sign-off readiness flows (SpyGlass or equivalent)

• Demonstrated ability to lead technically complex multi-team SoC programs

• Excellent debugging problem-solving and technical decision-making skills

• Strong background in low-power SoC architecture UPF and multi-power-domain design

• Experience with PowerArtist Power Compiler or similar power analysis tools

• Exposure to AI/ML accelerator-based SoCs and high-performance computing platforms

• Experience with FPGA prototyping emulation platforms and early silicon validation

• Prior experience in technical leadership subsystem ownership or design lead roles

• Lead next-generation ARM-based SoCs for AI-driven platforms

• Influence architecture performance power and scalability decisions

• Work at the intersection of deep silicon engineering and leadership

• Shape teams processes and silicon that go into real production
  
  #LI-AS1