Senior Manager Design Verification

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Build lead and scale a high-performing verification organization spanning DV emulation and AMS verification and behavioral model development of analog blocks.

• Own and drive the overall verification vision roadmap and execution for UCIe IP and subsystems across multiple product generations.

• Ensure high-quality on-time delivery of IP through rigorous IP-level and subsystem-level verification.

• Define and execute DV formal emulation and post-silicon validation strategies with a strong zero-defect and first-silicon-success mindset.

• Establish clear verification sign-off criteria coverage goals and quality metrics aligned with product and business objectives.

• Stay abreast of industry trends in verification and UCIe ecosystem standards translating them into competitive advantage.

• Partner closely with Architecture Design DFT Physical Design Firmware System and Silicon Validation teams to align requirements and execution

What Were Looking For

• Bachelors degree in computer science Electrical Engineering or related fields with 15 years of experience.

• Strong background in high-speed interconnect or protocol IP (UCIe PCIe CXL Ethernet SerDes or similar).

• Proven track record of delivering complex IP or SoCs to silicon with high quality and minimal escapes.

• exposure to post-silicon debug and validation with a track record of resolving complex silicon issues.

• Good understanding of SoC architecture processor cores memory and peripheral interfaces.

• Deep hands-on expertise in SystemVerilog/UVM coverage-driven verification formal verification and emulation.

• Excellent communication interpersonal and presentation skills.

• Strong cross-functional leadership skills.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.