Research Intern – CPU Microarchitecture and Memory Hierarchy
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Job Location:
Uster - Switzerland
Monthly Salary:
Not Disclosed
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships we have established leading end-to-end capabilities and strengths across the carrier networks enterprise consumer and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the worlds population.
With 20 sites across Europe and 1500 researchers Huaweis European Research Institute (ERI) oversees fundamental and applied technology research academic research cooperation projects and strategic technical planning across our network of European R&D facilities. Huaweis ERI includes the Von Neumann Research Center located in Zurich Switzerland. A major element of VNRC is a rapidly growing research laboratory focused on fundamental research in the area of computing systems (new hardware new software new algorithms).
The research work of the lab will be carried out not only by Huaweis internal research staff but also by our academic research partners in universities across Europe. The lab will provide an open research environment where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that like the best universities and research institutes is open and conducive to such world-leading scientific work.
The goal of this project is to improve performance efficiency of next-generation CPUs. The successful candidate will have the unique opportunity to work on groundbreaking ideas related to CPU microarchitecture and affect the future CPU products. Additionally we offer the opportunity to model and benchmark the performance of the proposed designs by using industry-class simulators and tools.
Responsibilities
Conduct research on next-generation CPU microarchitectures and memory hierarchies.
Modeling and evaluation of new microarchitectural features/designs using in-house and/or public simulators and frameworks.
Collaborate closely with researchers and product teams to align models with real world constraints.
Produce and present research papers at top-tier conferences and events as well as present the research findings to internal experts.
If the areas of CPU microarchitecture and cache/memory hierarchy looks interesting to you we are looking forward to receiving your application!
Minimum Requirements
Currently enrolled in a Masters or PhD program in Computer Science Computer Engineering or Electrical Engineering
Good knowledge of CPU architecture and memory hierarchies
Experience with architectural simulation platforms
Preferred Requirements
Currently enrolled in a PhD program in Computer Science Computer Engineering or Electrical Engineering
Hands-on experience with architectural simulation platforms
Experience with CPU architecture and memory hierarchies
Knowledge of hardware speculation mechanisms
Publications in relevant conferences and journals
Key Skills
- Robotics
- Machine Learning
- Python
- AI
- C/C++
- Data Collection
- Research Experience
- Signal Processing
- Natural Language Processing
- Computer Vision
- Deep Learning
- Tensorflow
