Senior Staff Engineer, Static Timing Analysis (STA) Engineer

Santa Clara County, CA - USA

Monthly Salary: Not Disclosed

Posted on: Yesterday

Vacancies: 1 Vacancy

Job Summary

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

The Design Center Engineering Physical Design team at Marvell in Santa Clara is seeking a Senior Staff Engineer Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projectsfrom artificial intelligence and machine learning to advanced wired and wireless infrastructureusing the latest technology team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance power and area (PPA) goals. This role involves close collaboration with Physical Design Design for Test (DFT) and other cross-functional teams across both local and global sites.

What You Can Expect

This role is based in Santa Clara CA. Relocation will be required if you are not already in the area. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
Perform timing analysis and closure on complex partitions
Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner
Implement/support multi-voltage designs through all aspects of implementation (place and route static timing physical verification) using industry standard EDA tools
Work with RTL design teams to drive assembly and design closure
Provide technical direction coaching and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes
Write scripts in Shell Python and TCL to extract data and achieve productivity enhancements through automation

What Were Looking For

If youre looking to apply your STA expertise in a dynamic and forward-thinking environment this is a great opportunity to explore.

Bachelors Masters or PhD degree in Electrical Engineering Computer Engineering or a related field.
8 years experience in back-end physical design and verification. Familiar with hierarchical physical design strategies methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow Verilog HDL synthesis and timing closure.
Expertise in full-chip & sub-hierarchy integration preferred
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in Perl tcl and Python
Strong knowledge in static timing analysis (Primetime preferred) and SDC timing constraints
Understanding of digital logic and computer architecture
Knowledge of Verilog
Good communication skills and self-discipline contributing in a team environment
Experience with multi-voltage and low-power design techniques is a plus
Experience with Cadence Innovus is preferred

Expected Base Pay Range (USD)

131010 - 196300 $ per annum

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional comprehensive benefits that support our employees at every stage - from internship to retirement and through lifes most important moments. Our offerings are built around four key pillars: financial well-being family support mental and physical health and recognition. Highlights include an employee stock purchase plan with a 2-year look back family support programs to help balance work and home life robust mental health resources to prioritize emotional well-being and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

#LI-VM1

Required Experience:

Staff IC

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.At Marvell you can affect the arc of individual lives ...

About Marvell

Your Team Your Impact

What You Can Expect

This role is based in Santa Clara CA. Relocation will be required if you are not already in the area. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
Perform timing analysis and closure on complex partitions
Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner
Implement/support multi-voltage designs through all aspects of implementation (place and route static timing physical verification) using industry standard EDA tools
Work with RTL design teams to drive assembly and design closure
Provide technical direction coaching and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes
Write scripts in Shell Python and TCL to extract data and achieve productivity enhancements through automation

What Were Looking For

If youre looking to apply your STA expertise in a dynamic and forward-thinking environment this is a great opportunity to explore.

Bachelors Masters or PhD degree in Electrical Engineering Computer Engineering or a related field.
8 years experience in back-end physical design and verification. Familiar with hierarchical physical design strategies methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow Verilog HDL synthesis and timing closure.
Expertise in full-chip & sub-hierarchy integration preferred
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in Perl tcl and Python
Strong knowledge in static timing analysis (Primetime preferred) and SDC timing constraints
Understanding of digital logic and computer architecture
Knowledge of Verilog
Good communication skills and self-discipline contributing in a team environment
Experience with multi-voltage and low-power design techniques is a plus
Experience with Cadence Innovus is preferred

Expected Base Pay Range (USD)

131010 - 196300 $ per annum

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

#LI-VM1

Required Experience:

Staff IC

Key Skills

Computer Science
Docker
Kubernetes
Python
VMware
C/C++
Go
System Architecture
gRPC
OS Kernels
Perl
Distributed Systems

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About Company

31 MSI

Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.

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