Design Verification Engineer
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Job Location:
Monthly Salary:
Posted on:
10 hours ago
Vacancies:
1 Vacancy
Job Summary
Greetings from Maneva!
Job Description
Job Title - Design Verification Engineer
Experience - 7-15 Years
Location - PAN India
Notice - Immediate to 15 Days
Responsibilities:
We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. to guarantee the success of our next-generation integrated circuits.
Responsibilities:
- Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM Formal Verification)
- Design and create high-quality verification environments (test benches) to achieve exceptional code coverage
- Utilize advanced verification tools (simulators formal verification tools) to thoroughly verify RTL functionality
- Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
- Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
- Lead and mentor junior DV engineers within the team fostering a collaborative and knowledge-sharing environment
- Participate in code reviews and champion best practices for verification code quality
- Stay current with the latest advancements in verification tools and methodologies
Qualifications:
- Bachelors degree in Electrical Engineering Computer Engineering or a related field (Masters degree a plus)
- 7-10 years of solid experience in Design Verification for ASICs or SoCs
- In-depth knowledge of digital design principles (combinational logic sequential logic finite state machines)
- Proven ability to develop debug and optimize complex verification environments
- Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM Formal)
- Extensive experience with simulation tools (ModelSim Cadence Incisive Synopsys VCS) and scripting languages (Python Perl)
- Experience with formal verification tools and techniques are a plus.
- Excellent analytical and problem-solving skills with a meticulous attention to detail.
- Strong communication collaboration and leadership skills to effectively contribute and guide the team.
If you are excited to grab this opportunity please apply directly or share your CV atand
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