Verification Lead Engineer

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profile Job Location:

Bengaluru - India

profile Monthly Salary: Not Disclosed
Posted on: 17 hours ago
Vacancies: 1 Vacancy

Job Summary

Lead Design Verification Engineer

Role Overview

We are looking for a hands-on Lead Design Verification Engineer to spearhead our functional verification this role you will not only architect complex verification environments from the ground up but also lead and mentor a talented team of 4-5 engineers. You will be the technical anchor for IP and SoC verification ensuring our designs meet the highest standards of functional correctness before tape-out.

Key Responsibilities Technical Leadership & Architecture
  • From-Scratch Development: Drive the architecture and implementation of UVM-based testbenches and verification components including drivers monitors and scoreboards from the ground up.

  • Verification Strategy: Lead the team in creating detailed test plans derived from design specifications and architecture documents.

  • Advanced Verification: Write directed and constrained-random test cases to ensure comprehensive functional correctness.

  • IP/SoC Oversight: Oversee IP and SoC verification projects focusing on protocol compliance and rigorous interface testing.

Team Management & Execution
  • Team Management: Directly manage a team of 4-5 DV engineers to execute complex projects on schedule.

  • Operational Excellence: Utilize EDA tools for simulation coverage analysis and regression management to maintain high productivity.

  • Quality Assurance: Lead code reviews participate in planning meetings and conduct internal training sessions to upskill the team.

Debug & Coverage Closure
  • Expert Debugging: Debug complex failures using waveforms and logs collaborating with design teams to root-cause critical issues.

  • Coverage Closure: Drive the team to achieve functional and code coverage goals performing deep-dive analysis into coverage holes to mitigate risk.

Required Skills & Qualifications
  • Technical Mastery: Extensive experience with SystemVerilog and UVM (Universal Verification Methodology).

  • Leadership: Proven track record of leading small to mid-sized engineering teams through full project lifecycles.

  • Problem Solving: Exceptional debugging skills and a deep understanding of RTL design and simulation flows.

  • Tools: Proficiency with industry-standard EDA tools (VCS Questa Xcelium) and waveform viewers (Verdi).

  • Communication: Ability to bridge the gap between architectural requirements and verification implementation.

Why Join Us
  • Opportunity to lead a high-impact team on cutting-edge silicon projects.

  • Collaborative environment where your technical decisions shape the final product.

  • Continuous learning through internal training and complex technical challenges.

Lead Design Verification Engineer Role Overview We are looking for a hands-on Lead Design Verification Engineer to spearhead our functional verification this role you will not only architect complex verification environments from the ground up but also lead and mentor a talented team of 4-5 enginee...
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