Engineer, ASIC Digital Design

Department Intro

Microns ASIC Logic Design team develops next-generation internally designed ASICs and controller IP that enable high-performance memory solutions. The team works across mature and deep sub-micron technology nodes and collaborates closely with analog verification physical design and validation partners to deliver robust production-ready designs.

Position Overview

As an ASIC Digital Design Engineer you will design and develop RTL for next-generation DRAM memory controllers and subsystems. You will work in a fast-paced highly technical environment interfacing with full-custom analog designs third-party IP and complex SystemVerilog blocks. This role includes multi-functional collaboration hands-on chip bring-up support and contributions to simulation and co-simulation efforts with opportunities to apply AI-enabled tooling within the design flow.

Responsibilities

• Design and develop RTL for next-generation DRAM memory controllers and subsystem blocks.
• Collaborate with full-custom analog design teams and integrate third-party IP and internal SystemVerilog blocks into cohesive digital solutions.
• Partner multi-functionally with Packaging Design Verification Analog Design Validation Synthesis and Physical Design teams to ensure end-to-end design success.
• Develop HDL models for circuits and participate in analog/digital co-simulation to validate functionality and interfaces.
• Support chip bring-up and lab validation activities including hands-on debug and issue resolution.
• Present technical concepts design approaches and implementation details clearly to design peers and multi-functional partners.
• Learn and utilize AI-enabled tools to improve efficiency and effectiveness within the ASIC design flow.

Minimum Qualifications

• Bachelors or Masters degree in Electrical Engineering or a closely related field.
• Strong fundamentals in logic design and RTL development using SystemVerilog.
• Understanding of verification techniques and high-speed I/O crossings.
• Strong written and verbal communication skills including ability to write and review architectural specifications and RTL.
• Experience with software programming and automation including Linux shell scripting and Python.
• Working knowledge of analog and mixed-signal concepts (CMOS/CML logic PLL DLL CDR).
• Collaborative curious approach with a consistent focus on learning contributing and growing.

Preferred Qualifications

• Experience with DRAM interfaces and memory-system RAS concepts (reliability availability serviceability).
• Familiarity with industry-standard tools for synthesis linting equivalency checking and formal verification.
• Experience participating in chip bring-up and lab validation including debug and root-cause isolation.
• Demonstrated interest in applying AI tools to improve productivity debug or design quality within ASIC development flows.