Staff Verification Engineer

Staff Verification Engineer

Cambridge UKFull-time PermanentHybrid

90000 to 115000(DOE) Bonus Benefits

The salary range for this role is broad as weare able toconsider varying levels of offer made will carefullytake into accountlevel of experience (including relevant industry experience) transferable relevantskillsandpreviousrelevant achievements.

Wewillalsoconsider part-timeapplicationsforthis role. Pleaseindicateyour preferred working schedulein yourcoverletter.

About us

Riverlanesmission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science to complex chemistry simulation for new drug design quantum computers will help humanity solve some of its most important challenges. But without QEC the industrys defining technical challenge such breakthroughs can never be the world leader in QEC technology. QEC is a complex problem that requires a range of skillstalentand passion.

We recently raised $75 million to accelerate ourcutting-edgeR& partner with many of the worlds leading quantum computing companies and governments to accelerate their path to utility-scale quantum remarkable progress and growing fast. Join us!

About the role

As a Staff Verification Engineer atRiverlane you will take ownership of verification across block subsystem and multi-FPGA system-level with hardware designers and embedded software engineers you willdeliver systems that are fully verified high-performing and trusted.

With visibility across the entire stack you willpartnerclosely with the Lead Verification Engineer todefine and delivertheverification strategy-from early design discussions through tofullsystem-level validation- ensuring every part of our technology meets the highest standards of performance and reliability.

You do not need a background in quantum computing! You will learn this along the way.

What you will do

As a key member of our verification team you will:

• Own the strategy and execution for block-level subsystem and multi-FPGA system designs.

• DevelopscalableUVM-based testbenches thatpush the boundaries of performance acrossacross multiple FPGAs andconfigurationsensuring our systems behave flawlessly in real-world conditions.

• Drive verification effortswith a sharp focus on risk coverage and system-levelbehaviour setting the bar for quality andestablishingbest practices that elevate the widerteam.

• Make pragmatic trade-offs tomaintainworld-class quality while keeping pace with innovation directly shaping the reliability and impact ofRiverlanescutting-edgetechnology.

What we need

Strong hands-onexpertiseinSystemVerilogand UVM.

• Experience verifying complex FPGA designs and integrations.

• Proven ability to debug across RTL simulation and hardware.

• Ability toworkeffectivelywith ambiguity and changing requirements.

• Demonstrable commercial experience in functional verification including ownership of verification planning and strategy.

• Exposure to different programming languages such as CCand Python.

• A proactive person who can independently define the scope of work.

• A collaborative personwith excellent communication skillswho actively shares(and listens to)constructivefeedback.

Even better ifyou have

• Formal verification experience.

• Experience mentoring junior verification engineers.

What can you expect from us

• A comprehensive benefits package that includesan annual bonus planprivate medical insurance life insurance and acontributory pension scheme

• Equity so that our team can share in the long-term success ofRiverlane

• 28 days annual leaveplus bank holidays and enhanced family leave

• A diverse work environment that brings together experts in many fields (including software and hardware development quantum information theoryphysicsand maths) and over 20 different nationalities

• A learning environment that encourages individual team and company growth anddevelopment including a regular programme of learning events and training and conference budgets

How to apply

Please upload a CV and covering letter by clicking ApplyNow. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role.

We review CVs as we receive them and interview as soon as we have applications thatlooklike a good match. We do not use closing dates. So pleaseapply as soon as possible to avoidmissing out onthis role.

If you have any queries please contact.

Everyone is welcome atRiverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age disability ethnicity gender gender reassignment religion or belief sexual orientation marital or civil partnership status or pregnancy and maternity/paternity.

Women and other underrepresented groups may be less likely to apply for a role unless they meet all ornearly allof the this applies to you we still encourage you to apply - you may be a great fit even if youdontmeet every single to hear from you.

If you need any adjustments made to the application or selection process so you can do your best please let us know. We will be happy to help.

Required Experience:

Staff IC