Senior Engineer I Design
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Job Location:
Monthly Salary:
Posted on:
2 hours ago
Vacancies:
1 Vacancy
Job Summary
Job Description:
The Wireless Solutions Group is seeking an experienced Senior Engineer I - Design for our next generation high-performance low-power wireless SoC and attach solutions. The role will include driving and optimizing synthesis constraints formal equivalence checks power optimization and static timing analysis using an industry leading SOC design flow. Successful candidate requires strong collaboration across sites and functions excellent communication and the ability to thrive in a fast-paced dynamic environment.
Key Responsibilities
Requirements/Qualifications:
0% - 25%
The Wireless Solutions Group is seeking an experienced Senior Engineer I - Design for our next generation high-performance low-power wireless SoC and attach solutions. The role will include driving and optimizing synthesis constraints formal equivalence checks power optimization and static timing analysis using an industry leading SOC design flow. Successful candidate requires strong collaboration across sites and functions excellent communication and the ability to thrive in a fast-paced dynamic environment.
Key Responsibilities
- Candidate will provide hands on technical contribution to the WSG Silicon Development Team in the area of design implementation.
- Drive and optimize Synthesis Formal constraints power optimization and STA for Microchips wireless SoC development.
- Work closely with digital analog and physical design teams to optimize front-end (RTL-to-Netlist) implementation for performance power and area.
- Drive front-end low power implementation and optimization using UPF.
- Familiarity with multi-mode and corner timing closure Signal integrity and noise analysis flows.
- Previous experience with Microcontroller design is desirable.
- Continuously improve RTL-to-Netlist tool flows and methodologies.
- Interfacing with external vendors and IP sources to resolve problems.
- Ability to work well in a team and excellent problem solving verbal and written communication skills.
- Working with members from international design and implementation teams
Requirements/Qualifications:
- Bachelors in an engineering discipline plus 5 years of experience or a Masters in an engineering discipline plus 2.5 years of experience.
- Expertise in Synthesis Formal Verification and Static Timing Analysis using industry leading tools.
- Familiarity with Verilog Verilog simulation and debug.
- Familiarity with Tcl Perl Python and Shell scripting.
- Solid understanding of digital implementation tools and flow
- Good Communication and teamwork skills
- Fluent in both written and spoken English
- Knowledge and exposure to complete Silicon Tapeout flow is desired
- We are looking for candidates who are self-motivators energetic and team players.
0% - 25%
Key Skills
- Electrical Engineering
- SOC
- PCB
- Warehouse Management
- Warehouse Experience
- CAD
- Creo
- SolidWorks
- Data Mining
- Digital design
- Mechanical Engineering
- Autocad
