Senior FPGA Design Engineer – 5G

Ottawa - Canada

Monthly Salary: $ 130000 - 180000

Posted on: 20 hours ago

Vacancies: 1 Vacancy

Job Summary

About Us:
Headquartered in Ottawa BTA Design serves the electronic design community from Canada specializing in ASIC and FPGA design and verification and embedded software development services. We augment and enhance our clients teams and accelerate the development of complete designs.

Were adaptable and efficient with a brilliant staff at our core. We aim to be the best at what we do.

Our success continues to fuel growth. We are currently searching globally for a number of key technical resources including a Senior FPGA Designer with exceptional technical skills and significant experience in 5G or related technologies.

Key Responsibilities:

Architect and RTL design complex IP blocks for 4G/5G Radio Units which are part of a system aligned with 3GPP and O-RAN Alliance specifications.
Carry out RTL logic design in Verilog or System Verilog FPGA synthesis and backend timing optimization and closure.
Ensure correct block and system functionality utilizing advanced UVM simulation verification techniques and system-level FPGA validation
Collaborate with the broader FPGA design team system level Radio Unit team and software team to ensure overall product integrity.

Key Qualifications:
The ideal individual is a senior/staff/principal FPGA Design Engineer with the following:

Minimum of an undergraduate degree in EE or equivalent skills/experience.
A minimum of 7 years of FPGA design experience in wireless or high-speed systems
Experience in cellular radio RAN 5G 4G LTE development
Experience with NR/LTE/eCPRI CPRI PTP protocols
Familiarity with JESD204B/C Ethernet PCIe AXI and high-speed SERDES
Modern FPGA development and tools experience across logic design synthesis PnR and timing closure.
Experience working with DSP algorithms and designs in MatLab/SimuLink and implementing them at high speed RTL in FPGA preferred.
Experience with high-speed FPGA design flow using Quartus Vivado MATLAB/Simulink HDL Coder
Experience in a lab environment troubleshooting issues up to the system level.
Block and chip level verification experience required UVM experience preferred
Experience with Git-based version control workflows
Track record as a self-starter a team player and a leader.

Compensation:
$130000 to $180000 plus company bonus and benefits plan.
Salary is heavily dependent on individual experience and capability.

This is a new position. Only candidates selected for an interview will be Intelligence tools are not used in the evaluation and selection of candidates.

Why Work Here
We offer interesting work in challenging stimulating technical environments with companies that lead the world in technology and innovation.

We recognize that our strength is in the individuals who join our team so at BTA Design Services we foster an environment where everyone is appreciated trusted and engaged. We recognize that work-life balance is important and we strive to provide our employees with challenging roles that also allow them to enjoy family friends and life outside of work.

Required Experience:

Senior IC

About Us:Headquartered in Ottawa BTA Design serves the electronic design community from Canada specializing in ASIC and FPGA design and verification and embedded software development services. We augment and enhance our clients teams and accelerate the development of complete designs.Were adaptable ...

Architect and RTL design complex IP blocks for 4G/5G Radio Units which are part of a system aligned with 3GPP and O-RAN Alliance specifications.
Carry out RTL logic design in Verilog or System Verilog FPGA synthesis and backend timing optimization and closure.
Ensure correct block and system functionality utilizing advanced UVM simulation verification techniques and system-level FPGA validation
Collaborate with the broader FPGA design team system level Radio Unit team and software team to ensure overall product integrity.

Key Qualifications:
The ideal individual is a senior/staff/principal FPGA Design Engineer with the following:

Minimum of an undergraduate degree in EE or equivalent skills/experience.
A minimum of 7 years of FPGA design experience in wireless or high-speed systems
Experience in cellular radio RAN 5G 4G LTE development
Experience with NR/LTE/eCPRI CPRI PTP protocols
Familiarity with JESD204B/C Ethernet PCIe AXI and high-speed SERDES
Modern FPGA development and tools experience across logic design synthesis PnR and timing closure.
Experience working with DSP algorithms and designs in MatLab/SimuLink and implementing them at high speed RTL in FPGA preferred.
Experience with high-speed FPGA design flow using Quartus Vivado MATLAB/Simulink HDL Coder
Experience in a lab environment troubleshooting issues up to the system level.
Block and chip level verification experience required UVM experience preferred
Experience with Git-based version control workflows
Track record as a self-starter a team player and a leader.