SoC Architect – Chiplet-Based Systems
Share
Job Location:
Monthly Salary:
Posted on:
3 days ago
Vacancies:
1 Vacancy
Job Summary
SoC Architect Chiplet-Based Systems
Locations: Bangalore /Remote ( any where India )
Job Description:
SoC Architect Chiplet-Based Systems
Job Description: Join us as a SoC Architect focusing on chiplet-based AI systems.
You will help define and drive the architecture of modular compute platforms using chiplet integration.
The position centers around architecting high-bandwidth I/O and memory connectivity between chiplets ensuring efficient partitioning of functionality and defining scalable inter-chiplet protocols for future-generation AI accelerators.
This role involves working closely with packaging PHY and interconnect experts to define die-to-die interfaces (e.g. UCIe BoW or custom links) and orchestrating integration across logic memory and I/O chiplets.
Youll also own subsystem architecture for PCIe RISC-V clusters and memory hierarchies while ensuring coherence and latency/power-optimized communication between disaggregated components.
Responsibilities: Define the SoC architecture for chiplet-based AI inference platforms including inter-chiplet data paths protocols and synchronization strategies. Drive partitioning decisions between compute I/O memory and control chiplets.
Architect PCIe and DMA interfaces that interact with host systems and bridge to chiplet domains. Specify die-to-die interconnect requirements (e.g. bandwidth latency power) and collaborate with packaging and PHY teams.
Integrate and verify third-party IPs for I/O memory and inter-chip communication.
Support bring-up and debug of multi-chip systems.
Required Background: BS/MS/Ph.D. in EE or CS with 10-25 years of SoC or multi-die system experience.
Hands-on experience in chiplet-based design including familiarity with UCIe EMIB Foveros or similar packaging technologies.
Strong understanding of modular SoC partitioning and die-to-die interconnect architectures.
Experience in PCIe Gen 4/5 RISC-V subsystems and high-performance memory interfaces (LPDDR4/5 HBM).
Familiarity with chiplet-aware system bring-up and verification methodologies.
SystemVerilog/UVM experience and knowledge of system-level test/debug strategies.
Key Skills
- APIs
- Pegasystems
- Spring
- SOAP
- .NET
- Hybris
- Solution Architecture
- Service-Oriented Architecture
- Adobe Experience Manager
- J2EE
- Java
- Oracle
