Silicon Design Package Engineer Tech M
Share
Job Location:
Santa Clara County, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
9 hours ago
Vacancies:
1 Vacancy
Job Summary
Role: Silicon Design Package Engineer
Location:Santa Clara CA
Location:Santa Clara CA
This role is highly specialized in semiconductor packaging design requiring strong EDA tool proficiency and knowledge of advanced packaging technologies
Tools & Knowledge:
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise:
Multi-layer package design experience.
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Flip-chip package design concepts
Tools & Knowledge:
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise:
Multi-layer package design experience.
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Flip-chip package design concepts
Key Skills
- Load & Unload
- Ruby
- Shipping & Receiving
- Forklift
- Lift Truck Experience
- Basic Math
- Packaging
- Warehouse Experience
- Delivery Driver Experience
- Heavy Lifting
- Human Resources
- RF Scanner
