Senior Signal Integrity Power Integrity (SIPI) Engineer

Who Youll Work With

Aristas cutting-edge Ethernet and optical networking platforms are built to push the limits of performance density and power efficiency. This wouldnt be possible without our Signal Integrity (SI) and Power Integrity (PI) engineers who design simulate and characterize interconnects enabling the fastest SerDes technologies in the industry. Were looking for a Senior Signal Integrity / Power Integrity Hardware Engineer to join our Hardware Design team at our headquarters in Santa Clara this role youll work at the intersection of advanced simulation next-generation SerDes (112G/224G/448G PAM4) and innovative routing packaging and power delivery techniques. Your work will directly influence the architecture and layout of Aristas next-generation Ethernet and optical systems for hyperscale AI and cloud networking.

What Youll Do

• Lead SI and PI efforts for high-speed electrical and optical interconnects across Aristas Ethernet platforms optical transceiver modules and high-density optical engines.
• Perform 3D EM design and simulation of high-speed interconnects (channels vias packages and connectors) for 112G/224G/448G PAM4 SerDes using tools such as Ansys HFSS SiWave Keysight ADS Cadence Sigrity CST and SiSoft QSI.
• Develop and validate test vehicles to characterize next-generation PCB materials packages and interconnects.
• Conduct S-parameter and time-domain measurements (VNA TDR BERT eye diagram jitter BER) to extract channel performance and validate modeling correlation.
• Perform link-level analysis for advanced standards (Ethernet 800G/1.6T PCIe Gen6/Gen7 CXL) using tools such as Keysight ADS or Cadence SystemSI.
• Design and optimize PCB stackups via structures breakout regions and connector transitions to meet compliance with IEEE CEI and MSA standards.
• Work closely with hardware mechanical optical ASIC and packaging teams to optimize stack-up breakout and routing strategies for high-density designs and ensure manufacturability and reliability.
• Define routing constraints reference plane designs and return path continuity for minimal signal degradation.
• Design and optimize PDNs to meet target impedance minimize noise coupling and support fast transient loads for high-speed DSPs and ICs.
• Provide SI/PI layout guidelines to PCB designers and review placement/routing for high-speed paths and power domains.
• Research and prototype novel materials backplane concepts and low-loss interconnect topologies to meet next-generation performance targets.
• Support bring-up and debug of production boards working cross-functionally to root-cause SI/PI-related issues.
• Engage with ASIC connector and packaging vendors to support co-design and channel optimization across multiple integration layers.
• Drive root cause analysis of SI/PI-related issues during validation and production builds.

Qualifications :

• B.S. or higher in Electrical Engineering Applied Physics or a related field with emphasis on electromagnetics signal integrity power integrity or high-speed digital design.
• 7 years of experience in SI/PI engineering for high-speed interconnects in optical networking or high-performance hardware systems.
• Solid understanding of signal integrity theory S-parameter analysis and channel modeling.
• Proven experience with 56G/112G/224G/448G PAM4 and NRZ serial links and related SI/PI challenges.
• Hands-on experience with 2.5D/3D EM solvers (Ansys HFSS SiWave Sigrity CST ADS).
• Strong lab skills using oscilloscopes VNAs TDRs BERTs and Ethernet compliance tools.
• Strong understanding of PCB stackup design via modeling impedance control and crosstalk mitigation.
• Familiarity with advanced PCB materials (e.g. Megtron 7 Tachyon 100G SLP) and manufacturing constraints for high-speed design.
• Experience with power delivery design including decoupling strategies PDN impedance analysis and noise mitigation techniques.
• Knowledge of power integrity and co-simulation techniques.
• Familiarity with transceiver MSA form factors (QSFP-DD OSFP) and standards from IEEE CEI and OIF.
• Excellent communication collaboration and documentation skills.

Preferred Qualifications

• M.E./ M.S. in Electrical Engineering or related field with emphasis on high-speed or mixed-signal systems.
• Experience with co-packaged optics chiplet-based architectures or advanced substrate technologies.
• Familiarity with EMI/EMC considerations and signal/power isolation in densely integrated photonic-electronic systems.
• Understanding of thermal and mechanical effects on SI/PI performance and long-term reliability.
• Experience working with fabrication vendors ASIC teams and contract manufacturers to ensure end-to-end channel integrity.

Additional Information :

Arista stands out as an engineering-centric company. Our leadership including founders and engineering managers are all engineers who understand sound software engineering principles and the importance of doing things right.
We hire globally into our diverse team. At Arista engineers have complete ownership of their projects. Our management structure is flat and streamlined and software engineering is led by those who understand it best. We prioritize the development and utilization of test automation tools.
Our engineers have access to every part of the company providing opportunities to work across various domains. Arista is headquartered in Santa Clara California with development offices in Australia Canada India Ireland and the US. We consider all our R&D centers equal in stature.
Join us to shape the future of networking and be part of a culture that values invention quality respect and fun.

Remote Work :

No

Employment Type :

Full-time