Required Skills and Qualifications:
- Education: Bachelors or Masters degree in Electrical Engineering Computer Science or a related field.
Experience:
- Proven experience in RTL design and integration (using Verilog VHDL or SystemVerilog).
- ARM core based design experience ARM SMMU design exposure and Python experience.
- Hands-on experience with digital design verification and subsystem integration.
- Experience with quality assurance tools and processes for RTL code.
- Knowledge of front-end design flow including synthesis linting and static analysis.
Technical Skills:
- Strong proficiency in RTL coding languages: Verilog VHDL or SystemVerilog.
- Experience with EDA tools (e.g. Cadence Synopsys Mentor Graphics).
- Familiarity with simulation tools (e.g. ModelSim VCS Xcelium).
- Experience with debugging and troubleshooting integration issues in RTL designs.
- Strong understanding of timing analysis and timing closure.
Soft Skills:
- Strong problem-solving and analytical skills.
- Ability to work in a fast-paced collaborative environment.
- Strong communication and documentation skills.
- Ability to prioritize tasks effectively and manage multiple deadlines.
Required Skills and Qualifications: Education: Bachelors or Masters degree in Electrical Engineering Computer Science or a related field. Experience: Proven experience in RTL design and integration (using Verilog VHDL or SystemVerilog). ARM core based design experience ARM SMMU design exposure an...
Required Skills and Qualifications:
- Education: Bachelors or Masters degree in Electrical Engineering Computer Science or a related field.
Experience:
- Proven experience in RTL design and integration (using Verilog VHDL or SystemVerilog).
- ARM core based design experience ARM SMMU design exposure and Python experience.
- Hands-on experience with digital design verification and subsystem integration.
- Experience with quality assurance tools and processes for RTL code.
- Knowledge of front-end design flow including synthesis linting and static analysis.
Technical Skills:
- Strong proficiency in RTL coding languages: Verilog VHDL or SystemVerilog.
- Experience with EDA tools (e.g. Cadence Synopsys Mentor Graphics).
- Familiarity with simulation tools (e.g. ModelSim VCS Xcelium).
- Experience with debugging and troubleshooting integration issues in RTL designs.
- Strong understanding of timing analysis and timing closure.
Soft Skills:
- Strong problem-solving and analytical skills.
- Ability to work in a fast-paced collaborative environment.
- Strong communication and documentation skills.
- Ability to prioritize tasks effectively and manage multiple deadlines.
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