Design Verification LeadEngineer || Onsite- Sunnyvale, CA ||
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Job Location:
Sunnyvale, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
Hope you are doing well
Please find the job description given below and let me know your interest.
Position: Design Verification Lead/Engineer
Location: Sunnyvale CA (Local Preferred; Relocation ok)
Duration: 12 Months
Job Description
Ensure functional correctness performance and adherence to specs for complex digital ASIC Core/IP designs with focus on unit and core-level verification.
Responsibilities:
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Develop detailed Core Verification Plans from micro-architecture and specifications.
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Architect and implement reusable robust verification environments in SystemVerilog/UVM.
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Create and run constrained-random and directed tests targeting high functional/code coverage.
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Analyze simulation results and debug complex failures in collaboration with design teams.
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Automate verification flow and regression management with Python/Perl scripts.
Requirements:
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Expert in SystemVerilog/UVM mandatory skill.
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Minimum 7 years hands-on experience.
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Strong knowledge of digital logic design and verification techniques.
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Experience verifying digital systems with standard IP (microprocessor cores hierarchical memory subsystems).
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Able to work independently and confidently engage with FE RTL designers and CPU/IP architects.
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Proficient with industry-standard EDA simulation and debugging tools.
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Strong debugging and root-cause analysis skills
Please share your updated resume and suggest the best number & time to connect with you
Thanks & Regard
| Yashwant Singh US IT Recruiter | E: |
