Design Verification LeadEngineer || Onsite- Sunnyvale, CA ||

Sunnyvale, CA - USA

Monthly Salary: Not Disclosed

Posted on: 8 hours ago

Vacancies: 1 Vacancy

Job Summary

Hope you are doing well

Please find the job description given below and let me know your interest.

Position: Design Verification Lead/Engineer
Location: Sunnyvale CA (Local Preferred; Relocation ok)
Duration: 12 Months

Job Description

Ensure functional correctness performance and adherence to specs for complex digital ASIC Core/IP designs with focus on unit and core-level verification.

Responsibilities:

Develop detailed Core Verification Plans from micro-architecture and specifications.
Architect and implement reusable robust verification environments in SystemVerilog/UVM.
Create and run constrained-random and directed tests targeting high functional/code coverage.
Analyze simulation results and debug complex failures in collaboration with design teams.
Automate verification flow and regression management with Python/Perl scripts.

Requirements:

Expert in SystemVerilog/UVM mandatory skill.
Minimum 7 years hands-on experience.
Strong knowledge of digital logic design and verification techniques.
Experience verifying digital systems with standard IP (microprocessor cores hierarchical memory subsystems).
Able to work independently and confidently engage with FE RTL designers and CPU/IP architects.
Proficient with industry-standard EDA simulation and debugging tools.
Strong debugging and root-cause analysis skills

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Thanks & Regard

Yashwant Singh
US IT Recruiter

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Hi Hope you are doing well Please find the job description given below and let me know your interest. Position: Design Verification Lead/Engineer Location: Sunnyvale CA (Local Preferred; Relocation ok) Duration: 12 Months Job Description Ensure functional correctness performance and adher...