Senior Principal Switch Architect

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

You will join the high-performance Teralynx Switch Architecture Team the group responsible for defining the architecture of Marvells next-generation data center switch ASICs. This team owns:
Product architecture definition
Behavioral modeling
Performance modeling & analysis
Architecture validation
Feature & protocol definition
Cross-functional technical leadership
You will collaborate directly with ASIC design SerDes firmware validation systems engineering and product teams to bring new switch architectures from concept to silicon and production.

Why Marvell Is an Employer of Choice
Cutting-edge networking silicon: Work on switch ASICs that define the next era of data center scale-out cloud fabrics and AI cluster interconnect.
Impact at industry scale: The architectures you design will be deployed across hyperscale data centers globally.
Technical leadership environment: Marvell empowers senior engineers to think big drive cross-functional alignment and influence long-term product direction.
Collaborative on-site culture: Daily in-person collaboration accelerates innovation strengthens technical rigor and enables rapid iteration.
Stability growth: Marvell continues to expand in high-growth markets including AI cloud carrier networks optical interconnects and custom silicon.

What You Can Expect

As a Senior Principal Engineer you will serve as a key technical leader driving architecture and execution for next-generation Teralynx switch products. You will:

• Define new features pipelines and protocolsfor next-generation data center switch chips.
• Deliver detailed behavioral and performance modelsto validate architectural decisions and ensure scalability for cloud-scale deployments.
• Drive end-to-end switch architecturefrom high-level concept through micro-architecture engagement and silicon bring-up.
• Partner with cross-functional engineering teams to ensure architectural intent is delivered through implementation and verification.
• Analyze tradeoffs across latency throughput memory architecture power area and QoSto guide design decisions.
• Participate in customer-facing technical discussions aligning product capabilities with real-world use cases and requirements.
• Contribute to long-term architectural direction and roadmap planningfor the Teralynx product line.
• Mentor engineers share best practices and elevate architectural rigor across the organization.

What You Can Expect

• High ownership and visibilityin defining and guiding major architectural features of Marvells flagship switch products.
• A deep hands-on role in shaping silicon that scales to the next generation of cloud and AI data centers.
• A highly collaborative on-site engineering culture that accelerates problem solving and innovation.
• Opportunities to work across domains hardware software systems and customer engineering broadening your technical influence.
• A stable environment with the resources of a global semiconductor leader paired with the agility of a fast-moving product organization.
• A compensation and benefits package designed to attract top technical talent.

What Were Looking For

• Bachelors degree in Computer Science Electrical Engineering Computer Engineering or related field and 15 years of relevant experience OR
• Masters/PhD with 1012 years of experiencein semiconductor architecture or ASIC development.
• Strong background designing or architecting complex ASICs ideally in networking or switch domains.
• Deep knowledge of Layer 2 / Layer 3 forwarding QoS congestion management and networking protocols.
• Expertise with behavioral and performance modeling architectural validation and system-level tradeoff analysis.
• Strong programming skills in C/C and Python.
• Demonstrated ability to collaborate effectively across geographies and multi-disciplinary engineering teams.
• Excellent communication skills with the ability to explain complex architectural concepts clearly and persuasively.

Preferred / Nice-to-Have

• Experience with multi-die / chiplet architectures die-to-die interfaces or advanced packaging.
• Familiarity with switch pipeline architectures buffer management traffic engineering and programmable datapaths.
• Experience engaging with customers or standards bodies.
• Published papers patents or previous leadership roles in architecture teams

Expected Base Pay Range (USD)

177380 - 265700 $ per annum

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell we offer a total compensation package including a base and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

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