Engineer Design Enablement Testsite
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Job Location:
Monthly Salary:
Posted on:
18 hours ago
Vacancies:
1 Vacancy
Job Summary
Аbout GlobalFoundries
GlobalFoundries is a world-leading contract manufacturer for the global semiconductor industry with facilities in Dresden Singapore New York and Vermont (USA). Our products are used in various technical applications e.g. mobile communications consumer electronics automotive and more. GlobalFoundries employs around 13000 people worldwide including 300 in Sofia.
Our Sofia based team will enhance GFs scale and capabilities while strengthening competitiveness of its specialized application solutions to further position the company for growth and value creation.
Our Design and Technology Enablement teams are working on the development of a broad portfolio of semiconductor technologies ranging from 350 nm down to 12nm including FD-SOI RF High-Voltage and automotive applications.
Responsibilities
- Design develop and utilize testsites which are in-house chip designs used to develop and understand the technology of interest.
- Design Lead for testsite content focused on advanced packaging technologies. Drive inputs from stakeholders and creates solutions for electrically testable structures that will be created through silicon processes. Use EDA tools for automated layout generation and verification that proper layout was created.
- Testsite coordinator role to drive tapeout readiness setup. Interact with various organizations involved in the tapeout setup and execution set schedules and ensure technical needs are answered by responsible groups across the organization so that the final testsite is delivered with all requirements met.
- Use the Skill language to write pCells and wiring scripts used in the design process
- Be able to understand and interpret DRC results on designs and collaborate with stakeholders to successfully resolve DRC issues
- Be able to work collaboratively across time zones to support the needs of stakeholders across the globe
- Be able to execute and debug internal automation which is used to create designs
- Be familiar with Cadence Virtuoso and Mentor Graphics Calibre tools
- Work and collaborate on other projects and/or assignments as needed
Required Qualifications
- Bachelors or Masters degree in Electronics Semiconductor Industry-related fields Physics or related disciplines
- Strong knowledge of chip design development workflows and verification flows
- Experience in design tools physical layout design and process/design interactions
- Excellent communication interpersonal and project management skills
- Understanding of design for manufacturing processesprogramming experience is a plus
We Offer
- Attractive compensation package with competitive salary performance related bonus plan and a global recognition program.
- Employee Stock Purchase Plan (including 20% match and 50 seed shares for first time participants non-executive).
- Individual technical or management career path opportunities supported by enhanced learning and development programs.
- Healthy and teambuilding work environment with various perks:
- Additional medical service including dental and coverage of employees children
- Food vouchers and canteen discounts
- Monthly budget for Flex benefit.
- Top-rated office location with recreation Spa facilities
- Discounts for Spa & Wellness Programs at NV Tower
- Regular Team Events and Celebrations
- Relocation/Immigration Support for international Hires
- Focus on employee work-life balance:
- Hybrid working model and flexible working time
- 21 to 25 days paid vacation depending on years with the company
Key Skills
- Mechanical Design
- SOC
- System Design
- GD&T
- CAD
- Creo
- SolidWorks
- Mechanical Engineering
- Perl
- Autocad
- HVAC Design
- Catia
About Company
Introducing GF Connect Seamlessly collaborate with GlobalFoundries to get to production and manage your orders faster and easier than ever. […]
