Overview:
TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.
Job Title: Performance Modeling/Verification Engineer - Intermediate
Work Location: Santa Clara CA 95054
Duration: 12 Months
Work Type: Temporary Assignment
Job Type: Hybrid
Job Description:
DUTIES:
- Develop enhance and maintain SystemC/TLM2 models for memory controllers peripherals and interconnects ensuring they accurately simulate the behavior and performance characteristics of the hardware.
- Collaborate with cross teams to integrate models into the tools used for system-level designs ensuring proper functionality and performance.
- Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
- Develop and execute testbenches to validate the functionality and correctness of models as well as participate in system-level testing and debugging.
- Create clear and comprehensive documentation for models including usage guidelines and design specifications.
Deliverables:
- Cycle approximate performance models
- SV/UVM Functional and Performance Verification
- Minimum 5 years of experience in SystemC.
- Recent and relevant experience with SystemC.
- Resume includes hands-on modeling projects using SystemC.
- Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.
- Experience in performance modeling and architecture exploration using SystemC.
- Ability to work with C integration since SystemC is built on C.
- Exposure to verification methodologies in SystemC (e.g. testbench creation simulation).
- Knowledge of modeling at different abstraction levels (e.g. behavioral RTL TLM).
EXPERIENCE AND EDUCATION:
- B.E/M.E/ or B.S/M.S in EE/CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modeling
- Proficiency in C/C programming.
- Understanding of memory controller architectures including DDR LPDDR and other relevant standards is preferred.
- UVM verification experience is preferred.
- Experience with debuggers and handling complex projects.
- Experience working in geographically dispersed teams; must be a strong team player.
- Knowledge of system-level architecture including buses like AXI/AHB and bridges is a plus.
- Familiarity with version control systems such as Perforce or Git.
TekWissen Group is an equal opportunity employer supporting workforce diversity.
Overview: TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors...
Overview:
TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.
Job Title: Performance Modeling/Verification Engineer - Intermediate
Work Location: Santa Clara CA 95054
Duration: 12 Months
Work Type: Temporary Assignment
Job Type: Hybrid
Job Description:
DUTIES:
- Develop enhance and maintain SystemC/TLM2 models for memory controllers peripherals and interconnects ensuring they accurately simulate the behavior and performance characteristics of the hardware.
- Collaborate with cross teams to integrate models into the tools used for system-level designs ensuring proper functionality and performance.
- Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
- Develop and execute testbenches to validate the functionality and correctness of models as well as participate in system-level testing and debugging.
- Create clear and comprehensive documentation for models including usage guidelines and design specifications.
Deliverables:
- Cycle approximate performance models
- SV/UVM Functional and Performance Verification
- Minimum 5 years of experience in SystemC.
- Recent and relevant experience with SystemC.
- Resume includes hands-on modeling projects using SystemC.
- Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.
- Experience in performance modeling and architecture exploration using SystemC.
- Ability to work with C integration since SystemC is built on C.
- Exposure to verification methodologies in SystemC (e.g. testbench creation simulation).
- Knowledge of modeling at different abstraction levels (e.g. behavioral RTL TLM).
EXPERIENCE AND EDUCATION:
- B.E/M.E/ or B.S/M.S in EE/CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modeling
- Proficiency in C/C programming.
- Understanding of memory controller architectures including DDR LPDDR and other relevant standards is preferred.
- UVM verification experience is preferred.
- Experience with debuggers and handling complex projects.
- Experience working in geographically dispersed teams; must be a strong team player.
- Knowledge of system-level architecture including buses like AXI/AHB and bridges is a plus.
- Familiarity with version control systems such as Perforce or Git.
TekWissen Group is an equal opportunity employer supporting workforce diversity.
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