Principal ASIC Design Engineer

Credo is engineering the future of high-speed connectivity for the AI-driven world.With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges we deliver industry-leading solutions that power the next generation of cloud AI and hyperscale data centers.

Credo is pioneering a systems-level approach to connectivity integrating hardware software and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment improving performance and reducing complexity across their infrastructure.

At Credo youll be part of a team of world-class technologists and engineers that thrive on pushing the limits of whats possible for some of the worlds most important companies. Our portfolio includes cutting edge solutions including our softwareoptical DSPs PCIe/CXL products SerDes IP and advanced Active Electrical Cables(AECs) all designed for maximum performance energy efficiency and scalability.

We foster a culture oftechnical excellence collaboration and continuous learning where your ideas can shape the future of connectivity. From silicon architects to systems engineers every role at Credo contributes to solving real-world problems at scale.

Join us and help us architect the next generation of disruptive networking technologies because at Credo We Connect.

About the Role

As a Principal ASIC Design Engineer you will be responsible for all aspects of front-end ASIC design including RTL implementation and verification of complex logic blocks. You will collaborate with PD DFT STA and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.

Responsibilities

• Design implement and debug complex logic blocks.
• Integrate complex IPs from internal and external vendors.
• Support front-end integration activities such as Lint CDC synthesis and ECO.
• Participate in design and code reviews to ensure quality.
• Develop functional tests/testbenches and run RTL and gate-level simulations.
• Work with verification DFT and physical design engineers to achieve successful tape-outs.
• Bring up validate and debug chip features; collaborate with software firmware and systems teams.

Basic Qualifications

• BS/MS degree in Electrical Engineering or Computer Science.
• 10 years of relevant ASIC design experience.
• Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Proficiency in Verilog/SystemVerilog RTL design.
• Knowledge of synthesis and static timing analysis.
• Experience developing testbenches and test cases; familiarity with UVM.
• Experience with gate-level simulations chip bring-up and validation.
• Proven track record of successful production tape-outs.

Preferred Qualifications

• Expertise in scripting languages (Python Tcl Perl Shell).
• Familiarity with DFT methodology and physical design flow.
• Hands-on experience with STA and timing closure.
• Strong problem-solving and planning skills.
• Excellent communication and collaboration abilities.

The base salary range for this position is $180000 $210000 a year. The base salary ultimately offered is determined through a review of education experience training skills qualifications and location. This position is also eligible for a discretionary bonus equity and a full range of medical and other benefits.

Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race color religion gender sex sexual orientation national origin genetic information age disability veteran status or any other legally protected basis.

If you have a disability or special need that requires accommodation to navigate our website or complete the application process email

Required Experience:

Staff IC