Analog Layout Staff Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Play a leading role in developing next-generation high-speed SerDes IPs as part of Marvells Central Engineering team using advanced FinFET technologies to deliver best-in-class analog IPs.
• Design and implement complex analog/mixed-signal layouts for SerDes ADCs PLLs bandgap references and LDOs across deep sub-micron CMOS FinFET and emerging GAA nodes using industry-standard tools (Cadence Virtuoso Mentor).
• Collaborate with circuit designers globally to translate schematics into efficient high-performance layouts and drive end-to-end ownership from floor planning to tape-out.
• Ensure physical verification closure by resolving DRC LVS ERC and antenna violations; perform EMIR analysis and implement fixes for IR drop and electromigration.
• Lead layout reviews mentor junior engineers and promote best practices optimization techniques and design rule compliance while fostering knowledge-sharing and process improvements.
• Stay ahead of evolving technologies and tools and develop automation scripts (Perl Tcl SKILL) to enhance productivity and consistency.

What Were Looking For

• Education: BE/ MS/ Electrical/Electronics Engineering Microelectronics or related fields; 610 years of experience in high-speed analog/custom layout development.
• Strong understanding of semiconductor process technologies device physics and layout effects in advanced nodes.
• Proven experience in full-custom circuit layout and verification including RC extraction physical verification (DRC LVS ERC DFM) and EMIR analysis.
• Hands-on expertise in mixed-signal/analog/high-speed layouts (SerDes ADC/DAC PLL etc.) across advanced FinFET technologies.
• Proficiency with Cadence Virtuoso and industry-standard EDA tools; scripting skills (Perl Tcl SKILL) for automation are a plus.
• Knowledge of critical layout techniquesmatching shielding clock routing power planning ESD and latch-up strategies.
• Ability to own the full development cycle: floorplanning layout verification and delivery.
• Excellent communication skills to collaborate with global teams and provide clear status updates.
• Self-motivated adaptable and eager to learn in a dynamic environment.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.